Task and function in testbenches in Verilog - Mini Project: Build & Apply

Task and function in testbenches

📖 Scenario: You are writing a testbench for a simple digital circuit. To keep your testbench clean and reusable, you want to use tasks and functions to organize repeated actions and calculations.

🎯 Goal: Build a Verilog testbench that uses a task to apply a reset signal and a function to calculate the parity of a 4-bit input. Then, display the parity result.

📋 What You'll Learn

Create a task named apply_reset that sets the reset signal high for 5 time units and then low.

Create a function named calc_parity that takes a 4-bit input and returns its even parity bit.

Use the apply_reset task in the initial block.

Call the calc_parity function with a 4-bit value and store the result.

Display the parity result using $display.

💡 Why This Matters

🌍 Real World

Using tasks and functions in testbenches helps organize your test code, making it easier to read and reuse when testing digital circuits.

💼 Career

Hardware engineers and verification engineers use tasks and functions in Verilog testbenches to automate testing and verify designs efficiently.

1

Create signals and initial block

Declare a reg signal named reset and a reg [3:0] signal named data_in. Also, create an initial block where you set data_in to 4'b1011.

Verilog

reg reset;
reg [3:0] data_in;

initial begin
    // Your code here
end

Hint

Use reg to declare signals and assign data_in inside the initial block.

2

Create a task to apply reset

Define a task named apply_reset that sets reset to 1, waits 5 time units using #5, then sets reset to 0.

Verilog

reg reset;
reg [3:0] data_in;

task apply_reset;
    // Your code here
endtask

initial begin
    data_in = 4'b1011;
end

Hint

Use task and endtask keywords. Use #5; to wait 5 time units.

3

Create a function to calculate parity

Define a function named calc_parity that takes a 4-bit input input_val and returns a 1-bit even parity. Use the XOR operator to calculate parity.

Verilog

reg reset;
reg [3:0] data_in;

function calc_parity;
    input [3:0] input_val;
    // Your code here
endfunction

task apply_reset;
    begin
        reset = 1;
        #5;
        reset = 0;
    end
endtask

initial begin
    data_in = 4'b1011;
end

Hint

Use the XOR reduction operator ^ to calculate parity of all bits.

4

Use task and function, then display parity

Inside the initial block, call the apply_reset task. Then declare a reg named parity and assign it the result of calc_parity(data_in). Finally, use $display to print "Parity of %b is %b" with data_in and parity.

Verilog

reg reset;
reg [3:0] data_in;

function calc_parity;
    input [3:0] input_val;
    begin
        calc_parity = ^input_val; // XOR reduction for even parity
    end
endfunction

task apply_reset;
    begin
        reset = 1;
        #5;
        reset = 0;
    end
endtask

initial begin
    data_in = 4'b1011;
    // Your code here
end

Hint

Call the task with apply_reset();. Declare reg parity; and assign it with calc_parity(data_in);. Use $display to print the result.

Practice

1. Which of the following is true about tasks in Verilog testbenches?

easy

A. Tasks cannot have input or output arguments.

B. Tasks can include timing controls like delays.

C. Tasks must always return a value.

D. Tasks are used only for synthesizable code.

Solution

1. Step 1: Understand the role of tasks

   Tasks in Verilog testbenches are used to group statements and can include timing controls such as delays.

2. Step 2: Compare tasks and functions

   Unlike functions, tasks do not return values but can have timing controls and input/output arguments.

3. Final Answer:

   Tasks can include timing controls like delays. -> Option B

4. Quick Check:

   Tasks allow delays = C [OK]

Hint: Remember: tasks can have delays; functions cannot. [OK]

Common Mistakes:

• Thinking tasks must return a value
• Assuming tasks cannot have arguments
• Confusing tasks with synthesizable modules

2. Which of the following is the correct syntax to define a function in Verilog testbench?

easy

A. function void my_func(); begin ... end endfunction

B. task integer my_func(); begin ... end endtask

C. function integer my_func(); begin ... return 1; end endfunction

D. function my_func(); begin ... end

Solution

1. Step 1: Identify function syntax

   Functions must specify a return type and use 'function' and 'endfunction' keywords.

2. Step 2: Check return statement and type

   function integer my_func(); begin ... return 1; end endfunction correctly defines a function returning integer and includes a return statement.

3. Final Answer:

   function integer my_func(); begin ... return 1; end endfunction -> Option C

4. Quick Check:

   Function syntax with return type and return statement = B [OK]

Hint: Functions need return type and return statement. [OK]

Common Mistakes:

• Using 'void' as function return type
• Defining functions with 'task' keyword
• Omitting 'endfunction' keyword

3. What is the output of this Verilog testbench code snippet?

module tb;
  integer result;
  initial begin
    result = add_two(5);
    $display("Result = %0d", result);
  end
  function integer add_two(input integer x);
    add_two = x + 2;
  endfunction
endmodule

medium

A. Result = 7

B. Result = 5

C. Result = 2

D. Syntax error

Solution

1. Step 1: Understand function call and return

   The function 'add_two' takes input 5 and returns 5 + 2 = 7.

2. Step 2: Check display output

   The $display prints the returned value stored in 'result', which is 7.

3. Final Answer:

   Result = 7 -> Option A

4. Quick Check:

   Function returns 5+2=7 = A [OK]

Hint: Functions return values; check the return expression. [OK]

Common Mistakes:

• Confusing function return with task behavior
• Ignoring the return value assignment
• Assuming syntax error due to missing semicolons

4. Identify the error in this Verilog task definition:

task display_msg;
  input string msg;
  begin
    #5 $display(msg);
  end
endtask

medium

A. Missing semicolon after task name.

B. Delay (#5) is not allowed inside tasks.

C. Tasks cannot have input arguments.

D. The input argument type 'string' is not supported in Verilog tasks.

Solution

1. Step 1: Check argument types in tasks

   Verilog does not support 'string' type as input argument in tasks; it uses reg or wire types.

2. Step 2: Verify delay usage and syntax

   Delay (#5) is allowed in tasks, and semicolon after task name is not required.

3. Final Answer:

   The input argument type 'string' is not supported in Verilog tasks. -> Option D

4. Quick Check:

   Verilog tasks don't support 'string' type = A [OK]

Hint: Use reg or wire, not string, for task inputs. [OK]

Common Mistakes:

• Thinking delays are disallowed in tasks
• Assuming tasks cannot have inputs
• Adding unnecessary semicolons after task name

5. You want to create a testbench helper that calculates the average of three integers and waits 10 time units before returning the result. Which is the best way to implement this in Verilog?

hard

A. Use a task that calculates average, includes a #10 delay, and returns the value via output argument.

B. Use a task that calculates average and returns the value using a return statement.

C. Use a function that calculates average and returns immediately without delay.

D. Use a function that calculates average and includes a #10 delay before returning.

Solution

1. Step 1: Understand timing control in tasks and functions

   Functions cannot have delays (#10), but tasks can include delays.

2. Step 2: Return value from task

   Tasks do not return values directly but can output results via output arguments.

3. Step 3: Choose correct implementation

   Use a task that calculates average, includes a #10 delay, and returns the value via output argument, matching requirements.

4. Final Answer:

   Use a task that calculates average, includes a #10 delay, and returns the value via output argument. -> Option A

5. Quick Check:

   Delay needs task + output arg = D [OK]

Hint: Use tasks for delays; functions can't delay. Return via output args. [OK]

Common Mistakes:

• Trying to put delay inside a function
• Expecting tasks to return values directly
• Ignoring output arguments for tasks