Synthesizable vs non-synthesizable constructs in Verilog - Visual Side-by-Side Comparison

Concept Flow - Synthesizable vs non-synthesizable constructs

Start Verilog Code

↓

Check Construct Type

↓

Synthesizable

↓

Can be mapped

↓

onto hardware

↓

Generate Hardware

↓

End

The flow shows how Verilog code is checked to see if it can be turned into hardware (synthesizable) or only used for simulation (non-synthesizable).

Execution Sample

Verilog

always @(posedge clk) begin
  count <= count + 1; // Synthesizable
end

initial begin
  $display("Start"); // Non-synthesizable
end

This code shows a synthesizable counter and a non-synthesizable display statement used only in simulation.

Execution Table

Step	Code Line	Construct Type	Action	Result
1	always @(posedge clk) begin	Synthesizable	Start sequential logic	Prepare hardware block
2	count <= count + 1;	Synthesizable	Increment counter	Hardware counter increments on clock
3	end	Synthesizable	End block	Hardware block defined
4	initial begin	Non-Synthesizable	Start simulation block	Runs only during simulation
5	$display("Start");	Non-Synthesizable	Print message	Message shown in simulation console
6	end	Non-Synthesizable	End block	Simulation block ends
7	End of code	-	-	Synthesizable parts mapped to hardware; non-synthesizable ignored by synthesis

💡 Code ends; synthesizer maps only synthesizable constructs to hardware; non-synthesizable used for simulation only.

Variable Tracker

Variable	Start	After Step 2	Final
count	0	1	1

Key Moments - 3 Insights

Why does the $display statement not become hardware?

Because $display is inside an initial block (see execution_table step 5), which is non-synthesizable and only runs during simulation.

Can the always block with posedge clk be synthesized?

Yes, as shown in execution_table steps 1-3, always @(posedge clk) is synthesizable and creates hardware sequential logic.

What happens to non-synthesizable code during synthesis?

Non-synthesizable code is ignored by the synthesis tool and only used for simulation, as noted in execution_table step 7.

Visual Quiz - 3 Questions

Look at the execution_table, what is the construct type of the line '$display("Start");' at step 5?

A Synthesizable

B Unknown

C Non-Synthesizable

D Both synthesizable and non-synthesizable

💡 Hint

Refer to execution_table row with Step 5 under 'Construct Type' column.

At which step does the synthesizable hardware counter increment?

A Step 1

B Step 2

C Step 5

D Step 6

💡 Hint

Check execution_table row for Step 2 under 'Action' and 'Result' columns.

If the initial block is removed, what changes in the synthesis output?

A No change; hardware remains the same

B Hardware counter is removed

C Synthesis fails due to missing initial block

D Simulation stops working

💡 Hint

Refer to execution_table step 7 about non-synthesizable code being ignored by synthesis.

Concept Snapshot

Synthesizable constructs: code that can be turned into hardware (e.g., always @(posedge clk)).
Non-synthesizable constructs: simulation-only code (e.g., initial blocks, $display).
Synthesizer ignores non-synthesizable code.
Use synthesizable code for hardware design.
Use non-synthesizable code for testbenches and simulation.
Always check which constructs your synthesis tool supports.

Full Transcript

This visual trace shows how Verilog code is divided into synthesizable and non-synthesizable parts. The always block triggered on the clock edge is synthesizable and creates hardware logic that increments a counter. The initial block with $display is non-synthesizable and only runs during simulation to print messages. During synthesis, only synthesizable constructs are converted into hardware. Non-synthesizable constructs are ignored by the synthesis tool and used only for simulation and testing. Understanding this difference helps you write code that can be turned into real hardware and code that helps test that hardware.

Practice

1. Which of the following Verilog constructs is non-synthesizable and used only for simulation?

easy

A. Module instantiations

B. Initial blocks (initial)

C. Continuous assignments (assign)

D. Always blocks (always)

Solution

1. Step 1: Understand the role of initial blocks

   initial blocks run once at simulation start and are not synthesizable into hardware.

2. Step 2: Compare with synthesizable constructs

   always blocks, assign statements, and module instantiations describe hardware and are synthesizable.

3. Final Answer:

   Initial blocks (initial) -> Option B

4. Quick Check:

   initial = Non-synthesizable [OK]

Hint: Remember: initial blocks only simulate, never synthesize [OK]

Common Mistakes:

• Confusing always with initial
• Thinking assign is non-synthesizable
• Assuming module instantiations are simulation-only

2. Which of the following is the correct syntax for a synthesizable always block sensitive to the positive edge of clock clk?

easy

A. always @(clk or reset) begin ... end

B. always @(clk) begin ... end

C. always @(negedge clk or posedge reset) begin ... end

D. always @(posedge clk) begin ... end

Solution

1. Step 1: Identify correct edge sensitivity

   Synthesizable clocked logic uses posedge clk or negedge clk to trigger on clock edges.

2. Step 2: Check syntax correctness

   always @(posedge clk) is correct; always @(clk) triggers on any change, which is not typical for clocked logic.

3. Final Answer:

   always @(posedge clk) begin ... end -> Option D

4. Quick Check:

   Use posedge clk for clock edge sensitivity [OK]

Hint: Use posedge or negedge for clock edges [OK]

Common Mistakes:

• Using level sensitivity instead of edge sensitivity
• Mixing clock and reset signals incorrectly
• Omitting begin and end for multiple statements

3. What will be the output of the following Verilog code snippet during simulation?

reg [3:0] count;
initial begin
  count = 0;
  #5 count = 4'b1010;
end
always @(posedge clk) begin
  count <= count + 1;
end

Assuming clk toggles every 1 time unit starting at 0.

medium

A. Count stays 0 until time 5, then becomes 10 and increments every clock cycle

B. Count increments every clock cycle starting from 0, then changes to 10 at time 5

C. Count increments every clock cycle starting from 0, ignoring the initial block

D. Count remains 0 throughout simulation

Solution

1. Step 1: Analyze initial block effect

   The initial block sets count to 0 at time 0, then to 10 at time 5 (delay #5).

2. Step 2: Analyze always block behavior

   The always block increments count on every positive clock edge, but the non-blocking assignment means the update happens after the clock edge, so the delayed assignment at time 5 overrides the count value at that time.

3. Final Answer:

   Count stays 0 until time 5, then becomes 10 and increments every clock cycle -> Option A

4. Quick Check:

   initial #delay executes after clock edges [OK]

Hint: Delayed initial affects count after clock increments [OK]

Common Mistakes:

• Ignoring the initial block's delayed assignment
• Assuming count increments from 10 immediately
• Confusing blocking and non-blocking assignments

4. Identify the error in the following Verilog code snippet that prevents synthesis:

always @(posedge clk) begin
  integer i;
  for (i = 0; i < 4; i = i + 1) begin
    data[i] = i;
  end
end

medium

A. Using an integer variable inside an always block for synthesis

B. Declaring a loop variable inside the always block

C. Using blocking assignment (=) instead of non-blocking (<=) inside always block

D. Using a for loop inside an always block is not synthesizable

Solution

1. Step 1: Check variable declarations and loop usage

   Declaring integer i inside the always block is allowed for synthesis as loop variable.

2. Step 2: Identify assignment type issue

   Using blocking assignment = inside clocked always block causes unintended behavior; non-blocking <= is required for registers.

3. Final Answer:

   Using blocking assignment (=) instead of non-blocking (<=) inside always block -> Option C

4. Quick Check:

   Use non-blocking (<=) in clocked always blocks [OK]

Hint: Use <= for registers inside clocked always blocks [OK]

Common Mistakes:

• Thinking loop variables cannot be declared inside always blocks
• Believing for loops are non-synthesizable
• Ignoring difference between blocking and non-blocking assignments

5. You want to create a synthesizable Verilog module that counts the number of times an input signal sig is high during clock cycles, but also print the count value for debugging during simulation. Which approach correctly separates synthesizable and non-synthesizable constructs?

hard

A. Use an always @(posedge clk) block to increment count and an initial block with $display to print count

B. Use an always @(posedge clk) block to increment count and a separate always block with $display to print count

C. Use a continuous assignment to increment count and initial block to print count

D. Use a task to increment count and a function to print count

Solution

1. Step 1: Identify synthesizable counting logic

   Counting on clock edges must be in an always @(posedge clk) block using non-blocking assignments.

2. Step 2: Identify non-synthesizable debugging code

   Printing with $display is simulation-only and must be placed in an initial or separate simulation-only block.

3. Final Answer:

   Use an always @(posedge clk) block to increment count and an initial block with $display to print count -> Option A

4. Quick Check:

   Separate hardware logic and simulation prints [OK]

Hint: Put printing in initial, counting in clocked always [OK]

Common Mistakes:

• Trying to print inside synthesizable always block
• Using continuous assignment for counting
• Confusing tasks/functions for simulation prints