Synthesizable vs non-synthesizable constructs in Verilog - Practice Questions

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a synthesizable always block

What is the output value of out after the following Verilog code runs for one clock cycle?

Assume clk is a clock signal and rst is an active-high reset.

Verilog

module test(input clk, input rst, input [3:0] in, output reg [3:0] out);
  always @(posedge clk or posedge rst) begin
    if (rst)
      out <= 4'b0000;
    else
      out <= in + 1;
  end
endmodule

A out remains unchanged regardless of clk or rst

B out becomes in - 1 after the clock edge if rst is low

C out immediately changes to in + 1 without waiting for clock

D out becomes in + 1 after the clock edge if rst is low

💡 Hint

Think about how the always block triggers on the positive edge of clk or rst.

The always block triggers on the positive edge of clk or rst. If rst is high, out resets to 0. Otherwise, on the clock edge, out updates to in + 1. This is synthesizable sequential logic.

❓ Predict Output

intermediate

Output of a non-synthesizable initial block

What happens when the following Verilog code is simulated?

Is this code synthesizable?

Verilog

module test;
  reg [3:0] count;
  initial begin
    count = 4'b1010;
    #10 count = 4'b0101;
  end
endmodule

A count is initialized to 1010 at time 0, then changes to 0101 after 10 time units; this is non-synthesizable

B count remains at 0000 because initial blocks are ignored

C count changes immediately to 0101 at time 0; synthesizable

D count causes a synthesis error due to # delay

💡 Hint

Consider what initial blocks and delays (#) mean in synthesis.

Initial blocks and delays (#) are used for simulation only and are not synthesizable. The code initializes count at time 0 and changes it after 10 time units during simulation.

🔧 Debug

advanced

Identify the non-synthesizable construct

Which line in the following Verilog code is non-synthesizable and why?

Verilog

module test(input clk, input rst, output reg [3:0] out);
  integer i;
  always @(posedge clk) begin
    for (i = 0; i < 4; i = i + 1) begin
      out[i] <= ~out[i];
    end
  end
endmodule

A The bitwise negation ~ operator is non-synthesizable

B The for loop inside always block is non-synthesizable

C The use of integer i for loop control is non-synthesizable

D The use of non-blocking assignments <= inside the loop is non-synthesizable

💡 Hint

Think about variable types allowed in synthesizable loops.

Using an integer variable for loop control in synthesizable code is not allowed because synthesis tools require loop variables to be constant or parameters. The for loop and bitwise negation are synthesizable, as is non-blocking assignment.

📝 Syntax

advanced

Which code snippet is synthesizable?

Which of the following Verilog code snippets is synthesizable and will not cause synthesis errors?

A always @(posedge clk) begin if (enable) out = in; end

B always @(posedge clk) begin if (enable) out <= in; end

C always @(posedge clk) begin out = #5 in; end

D always @(posedge clk) begin out <= in + #1 1; end

💡 Hint

Consider blocking vs non-blocking assignments and delay usage in synthesis.

Option B uses non-blocking assignment (<=) inside a clocked always block, which is synthesizable. Option B uses blocking assignment (=) which can cause issues in sequential logic. Options B and D use delays (#), which are not synthesizable.

🚀 Application

expert

Determine the number of items in a synthesizable array

Given the following Verilog code, how many elements does the synthesizable array mem contain after synthesis?

Verilog

module test(input clk, input [3:0] addr, input [7:0] data_in, output reg [7:0] data_out);
  reg [7:0] mem [0:15];
  always @(posedge clk) begin
    mem[addr] <= data_in;
    data_out <= mem[addr];
  end
endmodule

A 16 elements

B 15 elements

C 8 elements

D 256 elements

💡 Hint

Look at the array declaration range.

The array mem is declared from index 0 to 15, which means it contains 16 elements. This is synthesizable as a memory block.

Practice

1. Which of the following Verilog constructs is non-synthesizable and used only for simulation?

easy

A. Module instantiations

B. Initial blocks (initial)

C. Continuous assignments (assign)

D. Always blocks (always)

Solution

1. Step 1: Understand the role of initial blocks

   initial blocks run once at simulation start and are not synthesizable into hardware.

2. Step 2: Compare with synthesizable constructs

   always blocks, assign statements, and module instantiations describe hardware and are synthesizable.

3. Final Answer:

   Initial blocks (initial) -> Option B

4. Quick Check:

   initial = Non-synthesizable [OK]

Hint: Remember: initial blocks only simulate, never synthesize [OK]

Common Mistakes:

• Confusing always with initial
• Thinking assign is non-synthesizable
• Assuming module instantiations are simulation-only

2. Which of the following is the correct syntax for a synthesizable always block sensitive to the positive edge of clock clk?

easy

A. always @(clk or reset) begin ... end

B. always @(clk) begin ... end

C. always @(negedge clk or posedge reset) begin ... end

D. always @(posedge clk) begin ... end

Solution

1. Step 1: Identify correct edge sensitivity

   Synthesizable clocked logic uses posedge clk or negedge clk to trigger on clock edges.

2. Step 2: Check syntax correctness

   always @(posedge clk) is correct; always @(clk) triggers on any change, which is not typical for clocked logic.

3. Final Answer:

   always @(posedge clk) begin ... end -> Option D

4. Quick Check:

   Use posedge clk for clock edge sensitivity [OK]

Hint: Use posedge or negedge for clock edges [OK]

Common Mistakes:

• Using level sensitivity instead of edge sensitivity
• Mixing clock and reset signals incorrectly
• Omitting begin and end for multiple statements

3. What will be the output of the following Verilog code snippet during simulation?

reg [3:0] count;
initial begin
  count = 0;
  #5 count = 4'b1010;
end
always @(posedge clk) begin
  count <= count + 1;
end

Assuming clk toggles every 1 time unit starting at 0.

medium

A. Count stays 0 until time 5, then becomes 10 and increments every clock cycle

B. Count increments every clock cycle starting from 0, then changes to 10 at time 5

C. Count increments every clock cycle starting from 0, ignoring the initial block

D. Count remains 0 throughout simulation

Solution

1. Step 1: Analyze initial block effect

   The initial block sets count to 0 at time 0, then to 10 at time 5 (delay #5).

2. Step 2: Analyze always block behavior

   The always block increments count on every positive clock edge, but the non-blocking assignment means the update happens after the clock edge, so the delayed assignment at time 5 overrides the count value at that time.

3. Final Answer:

   Count stays 0 until time 5, then becomes 10 and increments every clock cycle -> Option A

4. Quick Check:

   initial #delay executes after clock edges [OK]

Hint: Delayed initial affects count after clock increments [OK]

Common Mistakes:

• Ignoring the initial block's delayed assignment
• Assuming count increments from 10 immediately
• Confusing blocking and non-blocking assignments

4. Identify the error in the following Verilog code snippet that prevents synthesis:

always @(posedge clk) begin
  integer i;
  for (i = 0; i < 4; i = i + 1) begin
    data[i] = i;
  end
end

medium

A. Using an integer variable inside an always block for synthesis

B. Declaring a loop variable inside the always block

C. Using blocking assignment (=) instead of non-blocking (<=) inside always block

D. Using a for loop inside an always block is not synthesizable

Solution

1. Step 1: Check variable declarations and loop usage

   Declaring integer i inside the always block is allowed for synthesis as loop variable.

2. Step 2: Identify assignment type issue

   Using blocking assignment = inside clocked always block causes unintended behavior; non-blocking <= is required for registers.

3. Final Answer:

   Using blocking assignment (=) instead of non-blocking (<=) inside always block -> Option C

4. Quick Check:

   Use non-blocking (<=) in clocked always blocks [OK]

Hint: Use <= for registers inside clocked always blocks [OK]

Common Mistakes:

• Thinking loop variables cannot be declared inside always blocks
• Believing for loops are non-synthesizable
• Ignoring difference between blocking and non-blocking assignments

5. You want to create a synthesizable Verilog module that counts the number of times an input signal sig is high during clock cycles, but also print the count value for debugging during simulation. Which approach correctly separates synthesizable and non-synthesizable constructs?

hard

A. Use an always @(posedge clk) block to increment count and an initial block with $display to print count

B. Use an always @(posedge clk) block to increment count and a separate always block with $display to print count

C. Use a continuous assignment to increment count and initial block to print count

D. Use a task to increment count and a function to print count

Solution

1. Step 1: Identify synthesizable counting logic

   Counting on clock edges must be in an always @(posedge clk) block using non-blocking assignments.

2. Step 2: Identify non-synthesizable debugging code

   Printing with $display is simulation-only and must be placed in an initial or separate simulation-only block.

3. Final Answer:

   Use an always @(posedge clk) block to increment count and an initial block with $display to print count -> Option A

4. Quick Check:

   Separate hardware logic and simulation prints [OK]

Hint: Put printing in initial, counting in clocked always [OK]

Common Mistakes:

• Trying to print inside synthesizable always block
• Using continuous assignment for counting
• Confusing tasks/functions for simulation prints