Synthesizable vs non-synthesizable constructs in Verilog - Interactive Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a synthesizable always block triggered on the positive edge of clk.

Verilog

always @([1]) begin
  q <= d;
end

Drag options to blanks, or click blank then click option'

Aposedge clk

Bposedge reset

Cclk

Dnegedge clk

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'clk' without edge specification causes a latch or combinational logic.

The always block triggers on the positive edge of clk, which is synthesizable for flip-flops.

2fill in blank

medium

Complete the code to create a synthesizable combinational always block sensitive to a and b.

Verilog

always @([1]) begin
  y = a & b;
end

Drag options to blanks, or click blank then click option'

Aa or b

Bposedge a

Cnegedge b

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock edges in combinational always blocks is non-synthesizable.

For combinational logic, the sensitivity list includes all inputs using 'or'.

3fill in blank

hard

Fix the error in the code to make the for loop synthesizable.

Verilog

reg [3:0] count;
integer i;
always @(posedge clk) begin
  for ([1] = 0; i < 4; i = i + 1) begin
    count[i] <= 1'b0;
  end
end

Drag options to blanks, or click blank then click option'

Acount

Bi

Cclk

Dj

Attempts:

3 left

💡 Hint

Common Mistakes

Using undeclared or wrong variable names in the for loop.

The loop variable must be declared and used consistently; here 'i' is the loop variable.

4fill in blank

hard

Fill both blanks to create a synthesizable if-else statement inside an always block.

Verilog

always @(posedge clk) begin
  if ([1]) begin
    q <= 1'b1;
  end else if ([2]) begin
    q <= 1'b0;
  end
end

Drag options to blanks, or click blank then click option'

Areset

Benable

C~reset

D~enable

Attempts:

3 left

💡 Hint

Common Mistakes

Using negated signals incorrectly causing non-synthesizable behavior.

The first condition checks reset, the second checks enable signal for control.

5fill in blank

hard

Fill all three blanks to create a synthesizable case statement inside an always block.

Verilog

always @(posedge clk) begin
  case ([1])
    2'b00: out <= [2];
    2'b01: out <= [3];
    default: out <= 1'b0;
  endcase
end

Drag options to blanks, or click blank then click option'

Asel

B1'b1

C1'b0

Denable

Attempts:

3 left

💡 Hint

Common Mistakes

Using non-synthesizable signals or expressions in case statement.

The case statement uses 'sel' to select output values 1 or 0.

Practice

1. Which of the following Verilog constructs is non-synthesizable and used only for simulation?

easy

A. Module instantiations

B. Initial blocks (initial)

C. Continuous assignments (assign)

D. Always blocks (always)

Solution

1. Step 1: Understand the role of initial blocks

   initial blocks run once at simulation start and are not synthesizable into hardware.

2. Step 2: Compare with synthesizable constructs

   always blocks, assign statements, and module instantiations describe hardware and are synthesizable.

3. Final Answer:

   Initial blocks (initial) -> Option B

4. Quick Check:

   initial = Non-synthesizable [OK]

Hint: Remember: initial blocks only simulate, never synthesize [OK]

Common Mistakes:

• Confusing always with initial
• Thinking assign is non-synthesizable
• Assuming module instantiations are simulation-only

2. Which of the following is the correct syntax for a synthesizable always block sensitive to the positive edge of clock clk?

easy

A. always @(clk or reset) begin ... end

B. always @(clk) begin ... end

C. always @(negedge clk or posedge reset) begin ... end

D. always @(posedge clk) begin ... end

Solution

1. Step 1: Identify correct edge sensitivity

   Synthesizable clocked logic uses posedge clk or negedge clk to trigger on clock edges.

2. Step 2: Check syntax correctness

   always @(posedge clk) is correct; always @(clk) triggers on any change, which is not typical for clocked logic.

3. Final Answer:

   always @(posedge clk) begin ... end -> Option D

4. Quick Check:

   Use posedge clk for clock edge sensitivity [OK]

Hint: Use posedge or negedge for clock edges [OK]

Common Mistakes:

• Using level sensitivity instead of edge sensitivity
• Mixing clock and reset signals incorrectly
• Omitting begin and end for multiple statements

3. What will be the output of the following Verilog code snippet during simulation?

reg [3:0] count;
initial begin
  count = 0;
  #5 count = 4'b1010;
end
always @(posedge clk) begin
  count <= count + 1;
end

Assuming clk toggles every 1 time unit starting at 0.

medium

A. Count stays 0 until time 5, then becomes 10 and increments every clock cycle

B. Count increments every clock cycle starting from 0, then changes to 10 at time 5

C. Count increments every clock cycle starting from 0, ignoring the initial block

D. Count remains 0 throughout simulation

Solution

1. Step 1: Analyze initial block effect

   The initial block sets count to 0 at time 0, then to 10 at time 5 (delay #5).

2. Step 2: Analyze always block behavior

   The always block increments count on every positive clock edge, but the non-blocking assignment means the update happens after the clock edge, so the delayed assignment at time 5 overrides the count value at that time.

3. Final Answer:

   Count stays 0 until time 5, then becomes 10 and increments every clock cycle -> Option A

4. Quick Check:

   initial #delay executes after clock edges [OK]

Hint: Delayed initial affects count after clock increments [OK]

Common Mistakes:

• Ignoring the initial block's delayed assignment
• Assuming count increments from 10 immediately
• Confusing blocking and non-blocking assignments

4. Identify the error in the following Verilog code snippet that prevents synthesis:

always @(posedge clk) begin
  integer i;
  for (i = 0; i < 4; i = i + 1) begin
    data[i] = i;
  end
end

medium

A. Using an integer variable inside an always block for synthesis

B. Declaring a loop variable inside the always block

C. Using blocking assignment (=) instead of non-blocking (<=) inside always block

D. Using a for loop inside an always block is not synthesizable

Solution

1. Step 1: Check variable declarations and loop usage

   Declaring integer i inside the always block is allowed for synthesis as loop variable.

2. Step 2: Identify assignment type issue

   Using blocking assignment = inside clocked always block causes unintended behavior; non-blocking <= is required for registers.

3. Final Answer:

   Using blocking assignment (=) instead of non-blocking (<=) inside always block -> Option C

4. Quick Check:

   Use non-blocking (<=) in clocked always blocks [OK]

Hint: Use <= for registers inside clocked always blocks [OK]

Common Mistakes:

• Thinking loop variables cannot be declared inside always blocks
• Believing for loops are non-synthesizable
• Ignoring difference between blocking and non-blocking assignments

5. You want to create a synthesizable Verilog module that counts the number of times an input signal sig is high during clock cycles, but also print the count value for debugging during simulation. Which approach correctly separates synthesizable and non-synthesizable constructs?

hard

A. Use an always @(posedge clk) block to increment count and an initial block with $display to print count

B. Use an always @(posedge clk) block to increment count and a separate always block with $display to print count

C. Use a continuous assignment to increment count and initial block to print count

D. Use a task to increment count and a function to print count

Solution

1. Step 1: Identify synthesizable counting logic

   Counting on clock edges must be in an always @(posedge clk) block using non-blocking assignments.

2. Step 2: Identify non-synthesizable debugging code

   Printing with $display is simulation-only and must be placed in an initial or separate simulation-only block.

3. Final Answer:

   Use an always @(posedge clk) block to increment count and an initial block with $display to print count -> Option A

4. Quick Check:

   Separate hardware logic and simulation prints [OK]

Hint: Put printing in initial, counting in clocked always [OK]

Common Mistakes:

• Trying to print inside synthesizable always block
• Using continuous assignment for counting
• Confusing tasks/functions for simulation prints