SPI controller implementation in Verilog - Step-by-Step Execution

Concept Flow - SPI controller implementation

Start: Idle State

↓

Wait for Start Signal

↓

Load Data to Shift Register

↓

Shift Data Out Bit-by-Bit

↓

Toggle Clock Signal

↓

Receive Data Bit

↓

Check if All Bits Sent?

No→Shift Next Bit

Yes↓

Set Done Flag

↓

Return to Idle

The SPI controller waits for a start signal, loads data, shifts bits out while toggling clock, receives bits, and signals when done.

Execution Sample

Verilog

always @(posedge clk or negedge rst_n) begin
  if (!rst_n) state <= IDLE;
  else case(state)
    IDLE: if(start) state <= LOAD;
    LOAD: state <= TRANSFER;
    TRANSFER: if(bit_cnt == 7) state <= DONE;
    DONE: state <= IDLE;
  endcase
end

This code snippet shows the state transitions of the SPI controller on clock edges.

Execution Table

Step	State	start	bit_cnt	Action	Next State
1	IDLE	0	0	Waiting for start signal	IDLE
2	IDLE	1	0	Start signal received	LOAD
3	LOAD	1	0	Load data to shift register	TRANSFER
4	TRANSFER	1	0	Shift bit 0 out, bit_cnt=0	TRANSFER
5	TRANSFER	1	1	Shift bit 1 out, bit_cnt=1	TRANSFER
6	TRANSFER	1	2	Shift bit 2 out, bit_cnt=2	TRANSFER
7	TRANSFER	1	3	Shift bit 3 out, bit_cnt=3	TRANSFER
8	TRANSFER	1	4	Shift bit 4 out, bit_cnt=4	TRANSFER
9	TRANSFER	1	5	Shift bit 5 out, bit_cnt=5	TRANSFER
10	TRANSFER	1	6	Shift bit 6 out, bit_cnt=6	TRANSFER
11	TRANSFER	1	7	Shift bit 7 out, bit_cnt=7	DONE
12	DONE	1	7	Set done flag	IDLE

💡 After sending all 8 bits (bit_cnt=7), controller sets done flag and returns to IDLE.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7	After 8	After 9	After 10	After 11	Final
state	IDLE	IDLE	LOAD	TRANSFER	TRANSFER	TRANSFER	TRANSFER	TRANSFER	TRANSFER	TRANSFER	TRANSFER	DONE	IDLE
start	0	0	1	1	1	1	1	1	1	1	1	1	1
bit_cnt	0	0	0	0	1	2	3	4	5	6	7	7	7

Key Moments - 3 Insights

Why does the state stay in TRANSFER while bit_cnt is less than 7?

Because the controller needs to shift out all 8 bits one by one, it stays in TRANSFER state until bit_cnt reaches 7 as shown in steps 4 to 11 in the execution_table.

What triggers the transition from IDLE to LOAD state?

The start signal being 1 triggers the transition from IDLE to LOAD, as seen in step 2 of the execution_table.

Why does bit_cnt not increment in the LOAD state?

In LOAD state, the controller only loads data and does not shift bits yet, so bit_cnt remains 0, as shown in step 3.

Visual Quiz - 3 Questions

Look at the execution_table, what is the state at step 5?

A LOAD

B TRANSFER

C DONE

D IDLE

💡 Hint

Refer to row 5 in execution_table under 'State' column.

At which step does the bit_cnt reach 7?

A Step 9

B Step 12

C Step 11

D Step 7

💡 Hint

Check the 'bit_cnt' column in execution_table rows.

If start signal is never set to 1, what will be the final state after step 3?

A IDLE

B LOAD

C TRANSFER

D DONE

💡 Hint

Look at step 1 and 2 where start=0 keeps state in IDLE.

Concept Snapshot

SPI Controller Implementation in Verilog:
- Wait in IDLE until start signal is high
- Load data into shift register in LOAD state
- Shift data bit-by-bit in TRANSFER state while toggling clock
- Increment bit counter each shift
- When all bits sent (bit_cnt=7), go to DONE
- Set done flag and return to IDLE
- Use state machine with states: IDLE, LOAD, TRANSFER, DONE

Full Transcript

This visual execution trace shows how an SPI controller implemented in Verilog works step-by-step. It starts in the IDLE state waiting for a start signal. When start is 1, it moves to LOAD state to load data. Then it enters TRANSFER state where it shifts out bits one by one, incrementing a bit counter each time. After sending all 8 bits (bit_cnt reaches 7), it moves to DONE state to set a done flag and then returns to IDLE. The execution table tracks state, start signal, bit counter, and actions at each step. Variable tracker shows how state and bit counter change over time. Key moments clarify common confusions about state transitions and bit counting. The quiz tests understanding of state changes and bit counter values. This helps beginners see exactly how the SPI controller moves through states and handles data shifting.

Practice

1. What is the main role of the cs (chip select) signal in an SPI controller?

easy

A. To enable communication with the specific SPI device

B. To provide the clock signal for data transfer

C. To send data from master to slave

D. To receive data from the slave device

Solution

1. Step 1: Understand the function of cs in SPI

   The cs signal is used to select which SPI device the master wants to communicate with by enabling it.

2. Step 2: Differentiate cs from other signals

   The clock signal is sclk, data sent from master is mosi, and data received is miso. So cs is not for clock or data transfer but device selection.

3. Final Answer:

   To enable communication with the specific SPI device -> Option A

4. Quick Check:

   cs = device enable [OK]

Hint: Remember: cs selects device, sclk clocks data [OK]

Common Mistakes:

• Confusing cs with clock signal
• Thinking cs sends or receives data
• Mixing up mosi and miso signals

2. Which of the following is the correct Verilog syntax to declare a 8-bit register named shift_reg?

easy

A. reg shift_reg:8;

B. reg shift_reg[7:0];

C. wire [7:0] shift_reg;

D. reg [7:0] shift_reg;

Solution

1. Step 1: Recall Verilog register declaration syntax

   Registers are declared with reg [width-1:0] name; format. For 8 bits, it is [7:0].

2. Step 2: Check each option

   reg [7:0] shift_reg; uses correct syntax. reg shift_reg[7:0]; reverses the range and name. wire [7:0] shift_reg; uses wire, not reg. reg shift_reg:8; uses invalid colon syntax.

3. Final Answer:

   reg [7:0] shift_reg; -> Option D

4. Quick Check:

   reg [7:0] name; = correct reg declaration [OK]

Hint: Use reg [7:0] name; for 8-bit registers [OK]

Common Mistakes:

• Using wire instead of reg for storage
• Incorrect bit range syntax
• Misplacing brackets around name

3. Given this snippet of an SPI controller shift register update inside a clocked always block:

always @(posedge sclk) begin
  if (cs == 0) begin
    shift_reg <= {shift_reg[6:0], miso};
  end
end

What does this code do on each rising edge of sclk when cs is low?

medium

A. Loads miso into the MSB of shift_reg without shifting

B. Shifts shift_reg right by 1 and inserts miso at MSB

C. Shifts shift_reg left by 1 and inserts miso at LSB

D. Clears shift_reg to zero

Solution

1. Step 1: Analyze the shift operation

   The code concatenates shift_reg[6:0] (bits 6 down to 0) with miso at the right side, effectively shifting left by 1 bit and inserting miso at the least significant bit (LSB).

2. Step 2: Confirm behavior when cs is low

   The shift happens only when cs == 0, which means the device is selected and data is being received bit by bit.

3. Final Answer:

   Shifts shift_reg left by 1 and inserts miso at LSB -> Option C

4. Quick Check:

   shift_reg <= {shift_reg[6:0], miso} = left shift + miso LSB [OK]

Hint: Concatenation {a,b} puts b at LSB, shifting left [OK]

Common Mistakes:

• Thinking it shifts right instead of left
• Confusing MSB and LSB positions
• Ignoring the condition on cs signal

4. Consider this Verilog snippet for SPI clock generation:

always @(posedge clk) begin
  if (cs == 0) begin
    sclk <= ~sclk;
  end else begin
    sclk <= 0;
  end
end

What is the main problem with this code?

medium

A. It toggles sclk on every clk edge, causing sclk frequency to be half of clk only when cs is low

B. It does not reset sclk properly when cs is high

C. It causes sclk to toggle asynchronously to clk

D. It will cause a synthesis error due to missing sensitivity list

Solution

1. Step 1: Understand clock toggling logic

   The code toggles sclk on every rising edge of clk if cs is low, effectively dividing the clock frequency by 2 during active communication.

2. Step 2: Identify the problem

   This behavior is expected for SPI clock generation. The code also resets sclk to 0 when cs is high, which is correct. There is no asynchronous toggling or sensitivity list issue.

3. Final Answer:

   It toggles sclk on every clk edge, causing sclk frequency to be half of clk only when cs is low -> Option A

4. Quick Check:

   sclk toggles at half clk frequency when cs=0 [OK]

Hint: Toggling sclk halves clk frequency during cs low [OK]

Common Mistakes:

• Thinking sclk toggles asynchronously
• Expecting sclk to run continuously
• Confusing sensitivity list with always block usage

5. You want to implement an SPI controller that sends 8 bits from a register tx_data over mosi and receives 8 bits into rx_data from miso. Which approach correctly handles the bit counting and shifting in Verilog?

hard

A. Use an 8-bit counter that decrements on each sclk falling edge when cs is high, shift tx_data right to output MSB on mosi, and shift in miso into rx_data.

B. Use a 3-bit counter that increments on each sclk rising edge when cs is low, shift tx_data left to output MSB on mosi, and shift in miso into rx_data.

C. Use a 4-bit counter that increments on each clk rising edge regardless of cs, shift tx_data right to output LSB on mosi, and ignore miso.

D. Use a 3-bit counter that resets only when cs is high, shift tx_data left to output LSB on mosi, and shift in miso into rx_data.

Solution

1. Step 1: Determine counter size and control

   For 8 bits, a 3-bit counter (0 to 7) is enough. It should increment on sclk rising edge only when cs is low (active communication).

2. Step 2: Understand shifting direction and data lines

   SPI usually sends MSB first, so shifting tx_data left outputs MSB on mosi. Incoming bits from miso are shifted into rx_data.

3. Step 3: Evaluate options

   Use a 3-bit counter that increments on each sclk rising edge when cs is low, shift tx_data left to output MSB on mosi, and shift in miso into rx_data. matches correct counter size, control, and shifting direction. Use a 4-bit counter that increments on each clk rising edge regardless of cs, shift tx_data right to output LSB on mosi, and ignore miso. uses wrong counter size and ignores miso. Use an 8-bit counter that decrements on each sclk falling edge when cs is high, shift tx_data right to output MSB on mosi, and shift in miso into rx_data. uses wrong edge and counter behavior. Use a 3-bit counter that resets only when cs is high, shift tx_data left to output LSB on mosi, and shift in miso into rx_data. incorrectly outputs LSB first and counter reset logic.

4. Final Answer:

   Use a 3-bit counter that increments on each sclk rising edge when cs is low, shift tx_data left to output MSB on mosi, and shift in miso into rx_data. -> Option B

5. Quick Check:

   3-bit counter + sclk rising + MSB first shift = correct SPI send/receive [OK]

Hint: Count 8 bits with 3-bit counter, shift MSB first [OK]

Common Mistakes:

• Using wrong counter size or clock edge
• Shifting in wrong direction for MSB first
• Ignoring chip select signal during counting