SPI controller implementation in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

SPI Controller State Machine Output

Given the following Verilog snippet for an SPI controller state machine, what is the value of spi_busy after the start signal is asserted and the state machine moves from IDLE to TRANSFER?

Verilog

typedef enum logic [1:0] {IDLE=2'b00, TRANSFER=2'b01, DONE=2'b10} state_t;

state_t state = IDLE;
logic spi_busy = 0;
logic start = 0;

always_ff @(posedge clk) begin
  case(state)
    IDLE: if(start) state <= TRANSFER;
    TRANSFER: state <= DONE;
    DONE: state <= IDLE;
  endcase
  spi_busy <= (state == TRANSFER);
end

A Remains at previous value

B 0

C 1

D Unknown (depends on clk timing)

💡 Hint

Remember that spi_busy is assigned after the state update in the same clock cycle.

The state variable updates on the clock edge, but spi_busy is assigned based on the old state value before the update. So when start is asserted, state changes from IDLE to TRANSFER, but spi_busy still sees the old state value, which is IDLE, so it remains 0 in that clock cycle.

🧠 Conceptual

intermediate

SPI Clock Polarity and Phase Settings

In an SPI controller, what do the clock polarity (CPOL) and clock phase (CPHA) settings control?

A CPOL and CPHA both control the chip select timing

B CPOL sets the data bit order; CPHA sets the clock frequency

C CPOL enables the SPI controller; CPHA resets the controller

D CPOL sets the idle clock level; CPHA sets when data is sampled relative to the clock edge

💡 Hint

Think about how SPI devices synchronize data with the clock.

CPOL defines whether the clock is idle high or low. CPHA defines whether data is sampled on the first or second clock edge. Together, they determine SPI mode.

🔧 Debug

advanced

Identify the Bug in SPI Shift Register

This Verilog code snippet is intended to shift out data on MOSI during SPI transfer. What is the bug that will cause incorrect data transmission?

Verilog

always_ff @(posedge spi_clk) begin
  if (start_transfer) begin
    shift_reg <= data_in;
  end else begin
    shift_reg <= {shift_reg[6:0], 1'b0};
  end
  mosi <= shift_reg[7];
end

A The MOSI bit is assigned after shifting, so it sends the wrong bit

B The shift register shifts left instead of right, reversing data order

C The clock edge used is incorrect for SPI mode

D The shift register is not loaded correctly on start_transfer

💡 Hint

Check the order of operations inside the always block.

The MOSI output is assigned after the shift operation, so it outputs the shifted bit, not the current MSB. MOSI should be assigned before shifting to send the correct bit.

📝 Syntax

advanced

Verilog Syntax for SPI Chip Select Control

Which of the following Verilog code snippets correctly implements active-low chip select (CS) control for an SPI controller?

A assign cs_n = (state == TRANSFER) ? 1'b0 : 1'b1;

B assign cs_n = (state == TRANSFER) ? 1 : 0;

C assign cs_n = (state == TRANSFER) ? 0 : 1'b1;

D assign cs_n = (state == TRANSFER) ? '0' : '1';

💡 Hint

Remember that active-low means the signal is 0 when active.

Option A uses correct bit values 1'b0 and 1'b1. Option A uses integers without bit width, which is allowed but less clear. Option A uses 0 without bit width, which is allowed but inconsistent. Option A uses character literals which are invalid in Verilog.

🚀 Application

expert

SPI Controller Bit Count After Transfer

An SPI controller shifts out 8 bits per transfer. The controller uses a 3-bit counter bit_cnt that increments on each SPI clock edge during transfer. After one full transfer, what is the value of bit_cnt?

Verilog

logic [2:0] bit_cnt = 0;
logic transfer_active = 1;

always_ff @(posedge spi_clk) begin
  if (transfer_active) begin
    bit_cnt <= bit_cnt + 1;
  end else begin
    bit_cnt <= 0;
  end
end

A 3'b1000 (decimal 8)

B 3'b000 (decimal 0)

C 3'b111 (decimal 7)

D 3'b001 (decimal 1)

💡 Hint

Consider the bit width of the counter and how it increments.

A 3-bit counter can count from 0 to 7. After 8 increments, it wraps back to 0. So after shifting out 8 bits, bit_cnt will be 7 (3'b111) on the last bit, then next increment resets or wraps.

Practice

1. What is the main role of the cs (chip select) signal in an SPI controller?

easy

A. To enable communication with the specific SPI device

B. To provide the clock signal for data transfer

C. To send data from master to slave

D. To receive data from the slave device

Solution

1. Step 1: Understand the function of cs in SPI

   The cs signal is used to select which SPI device the master wants to communicate with by enabling it.

2. Step 2: Differentiate cs from other signals

   The clock signal is sclk, data sent from master is mosi, and data received is miso. So cs is not for clock or data transfer but device selection.

3. Final Answer:

   To enable communication with the specific SPI device -> Option A

4. Quick Check:

   cs = device enable [OK]

Hint: Remember: cs selects device, sclk clocks data [OK]

Common Mistakes:

• Confusing cs with clock signal
• Thinking cs sends or receives data
• Mixing up mosi and miso signals

2. Which of the following is the correct Verilog syntax to declare a 8-bit register named shift_reg?

easy

A. reg shift_reg:8;

B. reg shift_reg[7:0];

C. wire [7:0] shift_reg;

D. reg [7:0] shift_reg;

Solution

1. Step 1: Recall Verilog register declaration syntax

   Registers are declared with reg [width-1:0] name; format. For 8 bits, it is [7:0].

2. Step 2: Check each option

   reg [7:0] shift_reg; uses correct syntax. reg shift_reg[7:0]; reverses the range and name. wire [7:0] shift_reg; uses wire, not reg. reg shift_reg:8; uses invalid colon syntax.

3. Final Answer:

   reg [7:0] shift_reg; -> Option D

4. Quick Check:

   reg [7:0] name; = correct reg declaration [OK]

Hint: Use reg [7:0] name; for 8-bit registers [OK]

Common Mistakes:

• Using wire instead of reg for storage
• Incorrect bit range syntax
• Misplacing brackets around name

3. Given this snippet of an SPI controller shift register update inside a clocked always block:

always @(posedge sclk) begin
  if (cs == 0) begin
    shift_reg <= {shift_reg[6:0], miso};
  end
end

What does this code do on each rising edge of sclk when cs is low?

medium

A. Loads miso into the MSB of shift_reg without shifting

B. Shifts shift_reg right by 1 and inserts miso at MSB

C. Shifts shift_reg left by 1 and inserts miso at LSB

D. Clears shift_reg to zero

Solution

1. Step 1: Analyze the shift operation

   The code concatenates shift_reg[6:0] (bits 6 down to 0) with miso at the right side, effectively shifting left by 1 bit and inserting miso at the least significant bit (LSB).

2. Step 2: Confirm behavior when cs is low

   The shift happens only when cs == 0, which means the device is selected and data is being received bit by bit.

3. Final Answer:

   Shifts shift_reg left by 1 and inserts miso at LSB -> Option C

4. Quick Check:

   shift_reg <= {shift_reg[6:0], miso} = left shift + miso LSB [OK]

Hint: Concatenation {a,b} puts b at LSB, shifting left [OK]

Common Mistakes:

• Thinking it shifts right instead of left
• Confusing MSB and LSB positions
• Ignoring the condition on cs signal

4. Consider this Verilog snippet for SPI clock generation:

always @(posedge clk) begin
  if (cs == 0) begin
    sclk <= ~sclk;
  end else begin
    sclk <= 0;
  end
end

What is the main problem with this code?

medium

A. It toggles sclk on every clk edge, causing sclk frequency to be half of clk only when cs is low

B. It does not reset sclk properly when cs is high

C. It causes sclk to toggle asynchronously to clk

D. It will cause a synthesis error due to missing sensitivity list

Solution

1. Step 1: Understand clock toggling logic

   The code toggles sclk on every rising edge of clk if cs is low, effectively dividing the clock frequency by 2 during active communication.

2. Step 2: Identify the problem

   This behavior is expected for SPI clock generation. The code also resets sclk to 0 when cs is high, which is correct. There is no asynchronous toggling or sensitivity list issue.

3. Final Answer:

   It toggles sclk on every clk edge, causing sclk frequency to be half of clk only when cs is low -> Option A

4. Quick Check:

   sclk toggles at half clk frequency when cs=0 [OK]

Hint: Toggling sclk halves clk frequency during cs low [OK]

Common Mistakes:

• Thinking sclk toggles asynchronously
• Expecting sclk to run continuously
• Confusing sensitivity list with always block usage

5. You want to implement an SPI controller that sends 8 bits from a register tx_data over mosi and receives 8 bits into rx_data from miso. Which approach correctly handles the bit counting and shifting in Verilog?

hard

A. Use an 8-bit counter that decrements on each sclk falling edge when cs is high, shift tx_data right to output MSB on mosi, and shift in miso into rx_data.

B. Use a 3-bit counter that increments on each sclk rising edge when cs is low, shift tx_data left to output MSB on mosi, and shift in miso into rx_data.

C. Use a 4-bit counter that increments on each clk rising edge regardless of cs, shift tx_data right to output LSB on mosi, and ignore miso.

D. Use a 3-bit counter that resets only when cs is high, shift tx_data left to output LSB on mosi, and shift in miso into rx_data.

Solution

1. Step 1: Determine counter size and control

   For 8 bits, a 3-bit counter (0 to 7) is enough. It should increment on sclk rising edge only when cs is low (active communication).

2. Step 2: Understand shifting direction and data lines

   SPI usually sends MSB first, so shifting tx_data left outputs MSB on mosi. Incoming bits from miso are shifted into rx_data.

3. Step 3: Evaluate options

   Use a 3-bit counter that increments on each sclk rising edge when cs is low, shift tx_data left to output MSB on mosi, and shift in miso into rx_data. matches correct counter size, control, and shifting direction. Use a 4-bit counter that increments on each clk rising edge regardless of cs, shift tx_data right to output LSB on mosi, and ignore miso. uses wrong counter size and ignores miso. Use an 8-bit counter that decrements on each sclk falling edge when cs is high, shift tx_data right to output MSB on mosi, and shift in miso into rx_data. uses wrong edge and counter behavior. Use a 3-bit counter that resets only when cs is high, shift tx_data left to output LSB on mosi, and shift in miso into rx_data. incorrectly outputs LSB first and counter reset logic.

4. Final Answer:

   Use a 3-bit counter that increments on each sclk rising edge when cs is low, shift tx_data left to output MSB on mosi, and shift in miso into rx_data. -> Option B

5. Quick Check:

   3-bit counter + sclk rising + MSB first shift = correct SPI send/receive [OK]

Hint: Count 8 bits with 3-bit counter, shift MSB first [OK]

Common Mistakes:

• Using wrong counter size or clock edge
• Shifting in wrong direction for MSB first
• Ignoring chip select signal during counting