SPI controller implementation in Verilog - Mini Project: Build & Apply

SPI Controller Implementation

📖 Scenario: You are designing a simple SPI (Serial Peripheral Interface) controller module in Verilog. SPI is a common way for microcontrollers to communicate with sensors, memory chips, and other devices using a few wires.This project will guide you through creating a basic SPI controller that can send and receive 8-bit data over SPI lines.

🎯 Goal: Build a Verilog module named spi_controller that sends and receives 8-bit data using SPI protocol signals: sclk (clock), mosi (master out slave in), miso (master in slave out), and ss (slave select).The controller should have an input start signal to begin transmission, an 8-bit input data_in to send, and an 8-bit output data_out to receive data. It should also output a done signal when the transfer is complete.

📋 What You'll Learn

Create a register to hold the 8-bit data to send

Create a counter to track bits sent and received

Implement SPI clock generation and data shifting logic

Output the received 8-bit data and a done signal when transfer finishes

💡 Why This Matters

🌍 Real World

SPI controllers are used in embedded systems to communicate with sensors, memory chips, and other peripherals using a simple serial interface.

💼 Career

Understanding SPI controller design is important for hardware engineers and FPGA developers working on embedded systems and digital communication interfaces.

1

DATA SETUP: Define module and registers

Create a Verilog module named spi_controller with inputs clk, start, data_in (8-bit), and miso. Add outputs sclk, mosi, ss, data_out (8-bit), and done. Inside the module, declare a register shift_reg (8-bit) to hold data to send and a register bit_count (4-bit) to count bits sent.

Verilog

module spi_controller(
    input clk,
    input start,
    input [7:0] data_in,
    input miso,
    output reg sclk,
    output reg mosi,
    output reg ss,
    output reg [7:0] data_out,
    output reg done
);

// Your code here

endmodule

Hint

Define the module with all inputs and outputs exactly as named. Declare shift_reg and bit_count as registers inside the module.

2

CONFIGURATION: Initialize control signals

Inside the spi_controller module, add an initial block to set sclk to 0, ss to 1 (inactive), done to 0, and bit_count to 0 at the start.

Verilog

module spi_controller(
    input clk,
    input start,
    input [7:0] data_in,
    input miso,
    output reg sclk,
    output reg mosi,
    output reg ss,
    output reg [7:0] data_out,
    output reg done
);

    reg [7:0] shift_reg;
    reg [3:0] bit_count;

    initial begin
        // Your code here
    end

endmodule

Hint

Use an initial block to set the starting values of the control signals and counters.

3

CORE LOGIC: Implement SPI data transfer

Add an always @(posedge clk) block inside spi_controller. When start is high and bit_count is 0, load data_in into shift_reg, set ss low (active), clear done. On each clock, toggle sclk. On the falling edge of sclk, shift shift_reg left by 1, output the MSB on mosi, and read miso into data_out LSB. Increment bit_count. When bit_count reaches 8, set done high and ss high (inactive).

Verilog

module spi_controller(
    input clk,
    input start,
    input [7:0] data_in,
    input miso,
    output reg sclk,
    output reg mosi,
    output reg ss,
    output reg [7:0] data_out,
    output reg done
);

    reg [7:0] shift_reg;
    reg [3:0] bit_count;

    initial begin
        sclk = 0;
        ss = 1;
        done = 0;
        bit_count = 0;
    end

    always @(posedge clk) begin
        // Your code here
    end

endmodule

Hint

Use a clocked always block to toggle sclk and shift bits out and in. Remember to activate ss low during transfer and set done when finished.

4

OUTPUT: Display transfer completion

Add a always @(posedge clk) block outside the previous one that prints "SPI transfer done: data_out = 0xXX" when done is high, where XX is the hexadecimal value of data_out. Use $display for printing.

Verilog

module spi_controller(
    input clk,
    input start,
    input [7:0] data_in,
    input miso,
    output reg sclk,
    output reg mosi,
    output reg ss,
    output reg [7:0] data_out,
    output reg done
);

    reg [7:0] shift_reg;
    reg [3:0] bit_count;

    initial begin
        sclk = 0;
        ss = 1;
        done = 0;
        bit_count = 0;
    end

    always @(posedge clk) begin
        if (start && bit_count == 0) begin
            shift_reg <= data_in;
            ss <= 0;
            done <= 0;
            bit_count <= 0;
            sclk <= 0;
        end else if (ss == 0) begin
            sclk <= ~sclk;
            if (sclk == 1) begin
                mosi <= shift_reg[7];
            end else begin
                shift_reg <= {shift_reg[6:0], 1'b0};
                data_out <= {data_out[6:0], miso};
                bit_count <= bit_count + 1;
                if (bit_count == 7) begin
                    done <= 1;
                    ss <= 1;
                end
            end
        end
    end

    always @(posedge clk) begin
        // Your code here
    end

endmodule

Hint

Use another always @(posedge clk) block to check if done is high and print the received data using $display.

Practice

1. What is the main role of the cs (chip select) signal in an SPI controller?

easy

A. To enable communication with the specific SPI device

B. To provide the clock signal for data transfer

C. To send data from master to slave

D. To receive data from the slave device

Solution

1. Step 1: Understand the function of cs in SPI

   The cs signal is used to select which SPI device the master wants to communicate with by enabling it.

2. Step 2: Differentiate cs from other signals

   The clock signal is sclk, data sent from master is mosi, and data received is miso. So cs is not for clock or data transfer but device selection.

3. Final Answer:

   To enable communication with the specific SPI device -> Option A

4. Quick Check:

   cs = device enable [OK]

Hint: Remember: cs selects device, sclk clocks data [OK]

Common Mistakes:

• Confusing cs with clock signal
• Thinking cs sends or receives data
• Mixing up mosi and miso signals

2. Which of the following is the correct Verilog syntax to declare a 8-bit register named shift_reg?

easy

A. reg shift_reg:8;

B. reg shift_reg[7:0];

C. wire [7:0] shift_reg;

D. reg [7:0] shift_reg;

Solution

1. Step 1: Recall Verilog register declaration syntax

   Registers are declared with reg [width-1:0] name; format. For 8 bits, it is [7:0].

2. Step 2: Check each option

   reg [7:0] shift_reg; uses correct syntax. reg shift_reg[7:0]; reverses the range and name. wire [7:0] shift_reg; uses wire, not reg. reg shift_reg:8; uses invalid colon syntax.

3. Final Answer:

   reg [7:0] shift_reg; -> Option D

4. Quick Check:

   reg [7:0] name; = correct reg declaration [OK]

Hint: Use reg [7:0] name; for 8-bit registers [OK]

Common Mistakes:

• Using wire instead of reg for storage
• Incorrect bit range syntax
• Misplacing brackets around name

3. Given this snippet of an SPI controller shift register update inside a clocked always block:

always @(posedge sclk) begin
  if (cs == 0) begin
    shift_reg <= {shift_reg[6:0], miso};
  end
end

What does this code do on each rising edge of sclk when cs is low?

medium

A. Loads miso into the MSB of shift_reg without shifting

B. Shifts shift_reg right by 1 and inserts miso at MSB

C. Shifts shift_reg left by 1 and inserts miso at LSB

D. Clears shift_reg to zero

Solution

1. Step 1: Analyze the shift operation

   The code concatenates shift_reg[6:0] (bits 6 down to 0) with miso at the right side, effectively shifting left by 1 bit and inserting miso at the least significant bit (LSB).

2. Step 2: Confirm behavior when cs is low

   The shift happens only when cs == 0, which means the device is selected and data is being received bit by bit.

3. Final Answer:

   Shifts shift_reg left by 1 and inserts miso at LSB -> Option C

4. Quick Check:

   shift_reg <= {shift_reg[6:0], miso} = left shift + miso LSB [OK]

Hint: Concatenation {a,b} puts b at LSB, shifting left [OK]

Common Mistakes:

• Thinking it shifts right instead of left
• Confusing MSB and LSB positions
• Ignoring the condition on cs signal

4. Consider this Verilog snippet for SPI clock generation:

always @(posedge clk) begin
  if (cs == 0) begin
    sclk <= ~sclk;
  end else begin
    sclk <= 0;
  end
end

What is the main problem with this code?

medium

A. It toggles sclk on every clk edge, causing sclk frequency to be half of clk only when cs is low

B. It does not reset sclk properly when cs is high

C. It causes sclk to toggle asynchronously to clk

D. It will cause a synthesis error due to missing sensitivity list

Solution

1. Step 1: Understand clock toggling logic

   The code toggles sclk on every rising edge of clk if cs is low, effectively dividing the clock frequency by 2 during active communication.

2. Step 2: Identify the problem

   This behavior is expected for SPI clock generation. The code also resets sclk to 0 when cs is high, which is correct. There is no asynchronous toggling or sensitivity list issue.

3. Final Answer:

   It toggles sclk on every clk edge, causing sclk frequency to be half of clk only when cs is low -> Option A

4. Quick Check:

   sclk toggles at half clk frequency when cs=0 [OK]

Hint: Toggling sclk halves clk frequency during cs low [OK]

Common Mistakes:

• Thinking sclk toggles asynchronously
• Expecting sclk to run continuously
• Confusing sensitivity list with always block usage

5. You want to implement an SPI controller that sends 8 bits from a register tx_data over mosi and receives 8 bits into rx_data from miso. Which approach correctly handles the bit counting and shifting in Verilog?

hard

A. Use an 8-bit counter that decrements on each sclk falling edge when cs is high, shift tx_data right to output MSB on mosi, and shift in miso into rx_data.

B. Use a 3-bit counter that increments on each sclk rising edge when cs is low, shift tx_data left to output MSB on mosi, and shift in miso into rx_data.

C. Use a 4-bit counter that increments on each clk rising edge regardless of cs, shift tx_data right to output LSB on mosi, and ignore miso.

D. Use a 3-bit counter that resets only when cs is high, shift tx_data left to output LSB on mosi, and shift in miso into rx_data.

Solution

1. Step 1: Determine counter size and control

   For 8 bits, a 3-bit counter (0 to 7) is enough. It should increment on sclk rising edge only when cs is low (active communication).

2. Step 2: Understand shifting direction and data lines

   SPI usually sends MSB first, so shifting tx_data left outputs MSB on mosi. Incoming bits from miso are shifted into rx_data.

3. Step 3: Evaluate options

   Use a 3-bit counter that increments on each sclk rising edge when cs is low, shift tx_data left to output MSB on mosi, and shift in miso into rx_data. matches correct counter size, control, and shifting direction. Use a 4-bit counter that increments on each clk rising edge regardless of cs, shift tx_data right to output LSB on mosi, and ignore miso. uses wrong counter size and ignores miso. Use an 8-bit counter that decrements on each sclk falling edge when cs is high, shift tx_data right to output MSB on mosi, and shift in miso into rx_data. uses wrong edge and counter behavior. Use a 3-bit counter that resets only when cs is high, shift tx_data left to output LSB on mosi, and shift in miso into rx_data. incorrectly outputs LSB first and counter reset logic.

4. Final Answer:

   Use a 3-bit counter that increments on each sclk rising edge when cs is low, shift tx_data left to output MSB on mosi, and shift in miso into rx_data. -> Option B

5. Quick Check:

   3-bit counter + sclk rising + MSB first shift = correct SPI send/receive [OK]

Hint: Count 8 bits with 3-bit counter, shift MSB first [OK]

Common Mistakes:

• Using wrong counter size or clock edge
• Shifting in wrong direction for MSB first
• Ignoring chip select signal during counting