Gate-level delay annotation in Verilog - Step-by-Step Execution

Concept Flow - Gate-level delay annotation

Start Simulation

↓

Evaluate Gate Inputs

↓

Apply Delay Annotation

↓

Schedule Output Change After Delay

↓

Update Output Signal

↓

Continue Simulation

The simulation evaluates gate inputs, applies the specified delay, schedules the output change after that delay, then updates the output signal accordingly.

Execution Sample

Verilog

and #(3) G1 (out, in1, in2);
initial begin
  in1 = 0; in2 = 0;
  #5 in1 = 1;
  #5 in2 = 1;
end

This code models an AND gate with a 3-time-unit delay; inputs change over time and output updates after delay.

Execution Table

Step	Time (units)	Inputs (in1,in2)	Gate Output Evaluation	Scheduled Output Change	Output (out)
1	0	(0,0)	AND(0,0)=0	Output change at 0+3=3	0
2	3	(0,0)	Output updated to 0	None	0
3	5	(1,0)	AND(1,0)=0	Output change at 5+3=8	0
4	8	(1,0)	Output updated to 0	None	0
5	10	(1,1)	AND(1,1)=1	Output change at 10+3=13	0
6	13	(1,1)	Output updated to 1	None	1

💡 Simulation ends after last scheduled output update at time 13.

Variable Tracker

Variable	Time 0	Time 3	Time 5	Time 8	Time 10	Time 13
in1	0	0	1	1	1	1
in2	0	0	0	0	1	1
out	0	0	0	0	0	1

Key Moments - 2 Insights

Why does the output 'out' not change immediately when inputs change?

Because of the gate-level delay annotation #(3), the output change is scheduled 3 time units after input changes, as shown in execution_table rows 3 and 5.

What happens if inputs change again before the previous delay expires?

The output change is rescheduled based on the latest input change; previous scheduled changes are overridden, ensuring output updates reflect the latest inputs after delay.

Visual Quiz - 3 Questions

Look at the execution_table at Step 3 (Time 5). What is the scheduled output change time?

A 3

B 8

C 5

D 10

💡 Hint

Check the 'Scheduled Output Change' column at Step 3 in execution_table.

At which time does the output 'out' finally become 1?

A 13

B 10

C 8

D 5

💡 Hint

Look at the 'Output (out)' column in execution_table and find when it changes to 1.

If the delay #(3) was changed to #(5), when would the output update after inputs change at time 10?

A 13

B 10

C 15

D 20

💡 Hint

Add the new delay (5) to the input change time (10) to find the scheduled output change.

Concept Snapshot

Gate-level delay annotation syntax: gate_type #(delay) gate_name (out, in1, in2);
Delays specify how long after input change the output updates.
Simulation schedules output changes after delay, not immediately.
Multiple input changes reschedule output updates.
Used to model real hardware timing in Verilog.

Full Transcript

Gate-level delay annotation in Verilog adds a delay to gate output changes. When inputs change, the output does not update immediately but after the specified delay time. For example, an AND gate with #(3) delay updates its output 3 time units after inputs change. If inputs change again before the delay expires, the output update is rescheduled to reflect the latest inputs. This models real hardware timing accurately in simulations.

Practice

1. What is the purpose of gate-level delay annotation in Verilog?

easy

A. To define the input and output ports of a module

B. To declare variables in a module

C. To specify the time delay for signal propagation through a gate

D. To initialize registers with default values

Solution

1. Step 1: Understand gate-level delay annotation

   Gate-level delay annotation is used to add timing delays to logic gates in simulation.

2. Step 2: Identify its purpose

   This delay models the real-world time it takes for signals to propagate through gates, helping verify timing correctness.

3. Final Answer:

   To specify the time delay for signal propagation through a gate -> Option C

4. Quick Check:

   Gate delay = specify propagation time [OK]

Hint: Gate delays model real signal timing in simulation [OK]

Common Mistakes:

• Confusing delay annotation with variable declaration
• Thinking delay sets input/output ports
• Assuming delay initializes registers

2. Which of the following is the correct syntax to add a 5-time-unit delay to an AND gate in Verilog?

easy

A. and #(5) (out, in1, in2);

B. and #5 (out, in1, in2);

C. and delay(5) (out, in1, in2);

D. and (out, in1, in2) #5;

Solution

1. Step 1: Recall Verilog gate delay syntax

   The delay is specified immediately after the gate type using #delay without parentheses.

2. Step 2: Match correct syntax

   and #5 (out, in1, in2); uses 'and #5 (out, in1, in2);' which is the correct form.

3. Final Answer:

   and #5 (out, in1, in2); -> Option B

4. Quick Check:

   Delay after gate type with #number [OK]

Hint: Use #number immediately after gate type for delay [OK]

Common Mistakes:

• Using parentheses around delay value
• Placing delay after port list
• Writing delay as a function call

3. Given the following Verilog code snippet, what is the delay before out changes after in1 or in2 changes?

and #3 (out, in1, in2);

medium

A. 0 time units

B. 5 time units

C. 1 time unit

D. 3 time units

Solution

1. Step 1: Identify the delay annotation

   The code uses '#3' after the 'and' gate, indicating a 3-time-unit delay.

2. Step 2: Understand delay effect

   This means output changes occur 3 time units after input changes.

3. Final Answer:

   3 time units -> Option D

4. Quick Check:

   Delay #3 means 3 time units [OK]

Hint: Delay number equals output wait time after input change [OK]

Common Mistakes:

• Assuming delay is zero if not explicitly stated
• Confusing delay with input change time
• Choosing wrong delay value

4. Identify the error in the following Verilog gate-level delay annotation:

or (out, in1, in2) #4;

medium

A. Delay must be specified immediately after gate type, not after port list

B. Delay value cannot be 4

C. The gate type 'or' is invalid

D. Port list must be enclosed in square brackets

Solution

1. Step 1: Check delay placement

   Delay must come immediately after the gate type, not after the port list.

2. Step 2: Analyze given code

   The code places '#4' after the port list, which is incorrect syntax.

3. Final Answer:

   Delay must be specified immediately after gate type, not after port list -> Option A

4. Quick Check:

   Delay after gate type, not ports [OK]

Hint: Place #delay right after gate type, before ports [OK]

Common Mistakes:

• Putting delay after port list
• Using invalid gate names
• Wrong port list syntax

5. You want to model an AND gate with different rise and fall delays: 2 time units for rising output and 4 time units for falling output. Which is the correct Verilog gate-level delay annotation?

hard

A. and #(2,4) (out, in1, in2);

B. and #(4,2) (out, in1, in2);

C. and #(2) #(4) (out, in1, in2);

D. and #2 #4 (out, in1, in2);

Solution

1. Step 1: Understand Verilog rise/fall delay syntax

   Verilog allows specifying rise and fall delays as #(rise, fall) after the gate type.

2. Step 2: Match delays to correct order

   The first number is rise delay, second is fall delay, so #(2,4) means 2 units rise, 4 units fall.

3. Final Answer:

   and #(2,4) (out, in1, in2); -> Option A

4. Quick Check:

   Use #(rise, fall) for different delays [OK]

Hint: Use #(rise, fall) to set different delays [OK]

Common Mistakes:

• Reversing rise and fall values
• Using multiple # delays separately
• Incorrect syntax with multiple #