Gate-level delay annotation in Verilog - Mini Project: Build & Apply

Gate-level Delay Annotation in Verilog

📖 Scenario: You are designing a simple digital circuit in Verilog. To understand how fast your circuit works, you want to add delay annotations to the gates. This helps simulate the real time it takes for signals to pass through the gates.

🎯 Goal: You will create a Verilog module with basic gates and add gate-level delay annotations to each gate. Then, you will simulate the output to see the effect of delays.

📋 What You'll Learn

Create a Verilog module named delay_example with inputs a, b and output y.

Declare an internal wire w1.

Instantiate a NOT gate with a delay of 2 time units on input a to output w1.

Instantiate an AND gate with a delay of 3 time units on inputs w1 and b to output y.

Add a testbench module named testbench to apply inputs and display output y.

Simulate the design and observe the output changes with delays.

💡 Why This Matters

🌍 Real World

Gate-level delay annotation helps designers simulate real hardware timing, ensuring circuits work correctly at intended speeds.

💼 Career

Understanding gate delays is important for hardware engineers and FPGA/ASIC designers to optimize and verify digital circuits.

1

Create the module and declare inputs, outputs, and wire

Write a Verilog module named delay_example with inputs a, b and output y. Declare an internal wire called w1.

Verilog

module delay_example(input a, input b, output y);
    wire w1;
    // Your code here
endmodule

Hint

Use module keyword to start and endmodule to end. Declare inputs and outputs inside parentheses.

2

Add NOT gate with delay

Inside the delay_example module, instantiate a NOT gate with a delay of 2 time units. Connect input a to output w1 using this NOT gate.

Verilog

module delay_example(input a, input b, output y);
    wire w1;
    not #2 (w1, a);  // Your code here
endmodule

Hint

Use not #2 (output, input); syntax to add delay.

3

Add AND gate with delay

Inside the delay_example module, instantiate an AND gate with a delay of 3 time units. Connect inputs w1 and b to output y using this AND gate.

Verilog

module delay_example(input a, input b, output y);
    wire w1;
    not #2 (w1, a);
    and #3 (y, w1, b);  // Your code here
endmodule

Hint

Use and #3 (output, input1, input2); syntax to add delay.

4

Create testbench and display output

Write a testbench module named testbench. Declare reg variables a and b, and a wire y. Instantiate delay_example module. Apply these input values in sequence with 5 time units delay: a=0, b=0; then a=1; then b=1. Use $monitor to print a, b, and y. End simulation after 20 time units.

Verilog

module delay_example(input a, input b, output y);
    wire w1;
    not #2 (w1, a);
    and #3 (y, w1, b);
endmodule

module testbench;
    reg a, b;
    wire y;
    delay_example uut(a, b, y);
    initial begin
        // Your code here
    end
endmodule

Hint

Use initial block to apply inputs and $monitor to print values.

Practice

1. What is the purpose of gate-level delay annotation in Verilog?

easy

A. To define the input and output ports of a module

B. To declare variables in a module

C. To specify the time delay for signal propagation through a gate

D. To initialize registers with default values

Solution

1. Step 1: Understand gate-level delay annotation

   Gate-level delay annotation is used to add timing delays to logic gates in simulation.

2. Step 2: Identify its purpose

   This delay models the real-world time it takes for signals to propagate through gates, helping verify timing correctness.

3. Final Answer:

   To specify the time delay for signal propagation through a gate -> Option C

4. Quick Check:

   Gate delay = specify propagation time [OK]

Hint: Gate delays model real signal timing in simulation [OK]

Common Mistakes:

• Confusing delay annotation with variable declaration
• Thinking delay sets input/output ports
• Assuming delay initializes registers

2. Which of the following is the correct syntax to add a 5-time-unit delay to an AND gate in Verilog?

easy

A. and #(5) (out, in1, in2);

B. and #5 (out, in1, in2);

C. and delay(5) (out, in1, in2);

D. and (out, in1, in2) #5;

Solution

1. Step 1: Recall Verilog gate delay syntax

   The delay is specified immediately after the gate type using #delay without parentheses.

2. Step 2: Match correct syntax

   and #5 (out, in1, in2); uses 'and #5 (out, in1, in2);' which is the correct form.

3. Final Answer:

   and #5 (out, in1, in2); -> Option B

4. Quick Check:

   Delay after gate type with #number [OK]

Hint: Use #number immediately after gate type for delay [OK]

Common Mistakes:

• Using parentheses around delay value
• Placing delay after port list
• Writing delay as a function call

3. Given the following Verilog code snippet, what is the delay before out changes after in1 or in2 changes?

and #3 (out, in1, in2);

medium

A. 0 time units

B. 5 time units

C. 1 time unit

D. 3 time units

Solution

1. Step 1: Identify the delay annotation

   The code uses '#3' after the 'and' gate, indicating a 3-time-unit delay.

2. Step 2: Understand delay effect

   This means output changes occur 3 time units after input changes.

3. Final Answer:

   3 time units -> Option D

4. Quick Check:

   Delay #3 means 3 time units [OK]

Hint: Delay number equals output wait time after input change [OK]

Common Mistakes:

• Assuming delay is zero if not explicitly stated
• Confusing delay with input change time
• Choosing wrong delay value

4. Identify the error in the following Verilog gate-level delay annotation:

or (out, in1, in2) #4;

medium

A. Delay must be specified immediately after gate type, not after port list

B. Delay value cannot be 4

C. The gate type 'or' is invalid

D. Port list must be enclosed in square brackets

Solution

1. Step 1: Check delay placement

   Delay must come immediately after the gate type, not after the port list.

2. Step 2: Analyze given code

   The code places '#4' after the port list, which is incorrect syntax.

3. Final Answer:

   Delay must be specified immediately after gate type, not after port list -> Option A

4. Quick Check:

   Delay after gate type, not ports [OK]

Hint: Place #delay right after gate type, before ports [OK]

Common Mistakes:

• Putting delay after port list
• Using invalid gate names
• Wrong port list syntax

5. You want to model an AND gate with different rise and fall delays: 2 time units for rising output and 4 time units for falling output. Which is the correct Verilog gate-level delay annotation?

hard

A. and #(2,4) (out, in1, in2);

B. and #(4,2) (out, in1, in2);

C. and #(2) #(4) (out, in1, in2);

D. and #2 #4 (out, in1, in2);

Solution

1. Step 1: Understand Verilog rise/fall delay syntax

   Verilog allows specifying rise and fall delays as #(rise, fall) after the gate type.

2. Step 2: Match delays to correct order

   The first number is rise delay, second is fall delay, so #(2,4) means 2 units rise, 4 units fall.

3. Final Answer:

   and #(2,4) (out, in1, in2); -> Option A

4. Quick Check:

   Use #(rise, fall) for different delays [OK]

Hint: Use #(rise, fall) to set different delays [OK]

Common Mistakes:

• Reversing rise and fall values
• Using multiple # delays separately
• Incorrect syntax with multiple #