Gate-level delay annotation in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of gate-level delay annotated AND gate

What is the output waveform of the following Verilog code snippet with gate-level delay annotation?

module delay_and(input a, input b, output y);
  and #5 (y, a, b);
endmodule

// Inputs change at time 0: a=1, b=0; at time 3: b=1

Verilog

module delay_and(input a, input b, output y);
  and #5 (y, a, b);
endmodule

// Simulation input changes:
// time 0: a=1, b=0
// time 3: b=1

// Question: At what time does y change to 1?

A y changes to 1 at time 8

B y changes to 1 at time 5

C y changes to 1 at time 0

D y changes to 1 at time 3

💡 Hint

Remember the delay #5 means output changes 5 time units after inputs are stable.

The AND gate output changes 5 time units after both inputs are 1. Input b changes to 1 at time 3, so output changes at 3 + 5 = 8.

❓ Predict Output

intermediate

Output value with multiple gate delays

Given the following Verilog code with gate-level delays, what is the value of output z at time 10?

module delay_chain(input a, input b, output z);
  wire w;
  and #3 (w, a, b);
  not #4 (z, w);
endmodule

// Inputs: a=1, b=1 at time 0

Verilog

module delay_chain(input a, input b, output z);
  wire w;
  and #3 (w, a, b);
  not #4 (z, w);
endmodule

// Inputs a=1, b=1 at time 0
// Question: What is z at time 10?

A z changes at time 10 but value is undefined

B z is unknown (X)

C z = 0

D z = 1

💡 Hint

Calculate delays step by step: AND gate output then NOT gate output.

AND gate output w changes to 1 at time 3 (0+3). NOT gate output z changes 4 time units after w changes, so at time 7. Since w=1, z=0 inverted is 0, but NOT gate output is inverted, so z=0 at time 7. Wait, NOT gate output is inversion of w, so if w=1, z=0. So at time 10, z=0.

🔧 Debug

advanced

Identify error in gate-level delay annotation syntax

Which option contains a syntax error in gate-level delay annotation?

and #5 (y, a, b);

Verilog

and #5 (y, a, b);

A and #5 y, a, b;

B and # (5) (y, a, b);

C and #5 (y, a, b);

D and #(5) (y, a, b);

💡 Hint

Check the correct syntax for delay annotation in gate instantiation.

Option A misses parentheses around the port list, causing syntax error. Correct syntax requires parentheses around ports.

❓ Predict Output

advanced

Output waveform with multiple delays and input changes

Consider the following Verilog code with gate-level delays:

module complex_delay(input a, input b, output y);
  wire w;
  and #2 (w, a, b);
  or #3 (y, w, a);
endmodule

// Inputs change:
// time 0: a=0, b=0
// time 1: a=1
// time 4: b=1

What is the value of y at time 6?

Verilog

module complex_delay(input a, input b, output y);
  wire w;
  and #2 (w, a, b);
  or #3 (y, w, a);
endmodule

// Inputs:
// time 0: a=0, b=0
// time 1: a=1
// time 4: b=1

// Question: What is y at time 6?

A y changes at time 6 but value is undefined

B y = 0

C y is unknown (X)

D y = 1

💡 Hint

Calculate w and y values stepwise considering delays and input changes.

At time 1, a=1, b=0 so w remains 0 until b changes. b changes to 1 at time 4, so w changes to 1 at time 6 (4+2). The OR gate output y depends on w and a. At time 6, w just changed to 1, but OR gate delay is 3, so y will change at time 9. At time 6, y still reflects previous inputs, which are w=0 and a=1, so y=1. But since w=0 before 6, y= a OR w = 1 OR 0 = 1. Wait, OR gate delay is 3, so output changes 3 units after input changes. Inputs to OR at time 6 are w=0 (before change) and a=1, so y=1. So y=1 at time 6.

🧠 Conceptual

expert

Effect of gate-level delay annotation on simulation accuracy

Which statement best describes the effect of gate-level delay annotation in Verilog simulations?

A Gate-level delay annotation has no effect on simulation timing and is only for documentation.

B Gate-level delay annotation models the exact physical delay of gates, improving timing accuracy in simulations.

C Gate-level delay annotation causes synthesis tools to ignore the gate delays during hardware implementation.

D Gate-level delay annotation automatically adjusts delays based on input signal frequency.

💡 Hint

Think about why delays are added in gate-level simulation.

Gate-level delay annotation adds timing delays to gates in simulation to mimic real hardware delays, improving timing accuracy.

Practice

1. What is the purpose of gate-level delay annotation in Verilog?

easy

A. To define the input and output ports of a module

B. To declare variables in a module

C. To specify the time delay for signal propagation through a gate

D. To initialize registers with default values

Solution

1. Step 1: Understand gate-level delay annotation

   Gate-level delay annotation is used to add timing delays to logic gates in simulation.

2. Step 2: Identify its purpose

   This delay models the real-world time it takes for signals to propagate through gates, helping verify timing correctness.

3. Final Answer:

   To specify the time delay for signal propagation through a gate -> Option C

4. Quick Check:

   Gate delay = specify propagation time [OK]

Hint: Gate delays model real signal timing in simulation [OK]

Common Mistakes:

• Confusing delay annotation with variable declaration
• Thinking delay sets input/output ports
• Assuming delay initializes registers

2. Which of the following is the correct syntax to add a 5-time-unit delay to an AND gate in Verilog?

easy

A. and #(5) (out, in1, in2);

B. and #5 (out, in1, in2);

C. and delay(5) (out, in1, in2);

D. and (out, in1, in2) #5;

Solution

1. Step 1: Recall Verilog gate delay syntax

   The delay is specified immediately after the gate type using #delay without parentheses.

2. Step 2: Match correct syntax

   and #5 (out, in1, in2); uses 'and #5 (out, in1, in2);' which is the correct form.

3. Final Answer:

   and #5 (out, in1, in2); -> Option B

4. Quick Check:

   Delay after gate type with #number [OK]

Hint: Use #number immediately after gate type for delay [OK]

Common Mistakes:

• Using parentheses around delay value
• Placing delay after port list
• Writing delay as a function call

3. Given the following Verilog code snippet, what is the delay before out changes after in1 or in2 changes?

and #3 (out, in1, in2);

medium

A. 0 time units

B. 5 time units

C. 1 time unit

D. 3 time units

Solution

1. Step 1: Identify the delay annotation

   The code uses '#3' after the 'and' gate, indicating a 3-time-unit delay.

2. Step 2: Understand delay effect

   This means output changes occur 3 time units after input changes.

3. Final Answer:

   3 time units -> Option D

4. Quick Check:

   Delay #3 means 3 time units [OK]

Hint: Delay number equals output wait time after input change [OK]

Common Mistakes:

• Assuming delay is zero if not explicitly stated
• Confusing delay with input change time
• Choosing wrong delay value

4. Identify the error in the following Verilog gate-level delay annotation:

or (out, in1, in2) #4;

medium

A. Delay must be specified immediately after gate type, not after port list

B. Delay value cannot be 4

C. The gate type 'or' is invalid

D. Port list must be enclosed in square brackets

Solution

1. Step 1: Check delay placement

   Delay must come immediately after the gate type, not after the port list.

2. Step 2: Analyze given code

   The code places '#4' after the port list, which is incorrect syntax.

3. Final Answer:

   Delay must be specified immediately after gate type, not after port list -> Option A

4. Quick Check:

   Delay after gate type, not ports [OK]

Hint: Place #delay right after gate type, before ports [OK]

Common Mistakes:

• Putting delay after port list
• Using invalid gate names
• Wrong port list syntax

5. You want to model an AND gate with different rise and fall delays: 2 time units for rising output and 4 time units for falling output. Which is the correct Verilog gate-level delay annotation?

hard

A. and #(2,4) (out, in1, in2);

B. and #(4,2) (out, in1, in2);

C. and #(2) #(4) (out, in1, in2);

D. and #2 #4 (out, in1, in2);

Solution

1. Step 1: Understand Verilog rise/fall delay syntax

   Verilog allows specifying rise and fall delays as #(rise, fall) after the gate type.

2. Step 2: Match delays to correct order

   The first number is rise delay, second is fall delay, so #(2,4) means 2 units rise, 4 units fall.

3. Final Answer:

   and #(2,4) (out, in1, in2); -> Option A

4. Quick Check:

   Use #(rise, fall) for different delays [OK]

Hint: Use #(rise, fall) to set different delays [OK]

Common Mistakes:

• Reversing rise and fall values
• Using multiple # delays separately
• Incorrect syntax with multiple #