Design hierarchy for ALU in Verilog - Step-by-Step Execution

Concept Flow - Design hierarchy for ALU

Top Module: ALU

↓

Submodules:

↓

Adder

↓

Control Signals

↓

Output Result

The ALU top module connects submodules like Adder, Logic Unit, and Shifter, controlled by signals to produce the final output.

Execution Sample

Verilog

module ALU(input [3:0] A, input [3:0] B, input [1:0] Op, output reg [3:0] Result);
  wire [3:0] sum, logic_out, shift_out;
  Adder add(A, B, sum);
  LogicUnit logic_unit(A, B, logic_out);
  Shifter shifter(A, shift_out);

  always @(*) begin
    case(Op)
      2'b00: Result = sum;
      2'b01: Result = logic_out;
      2'b10: Result = shift_out;
      default: Result = 4'b0000;
    endcase
  end
endmodule

This ALU module uses submodules Adder, LogicUnit, and Shifter, selecting output based on Op code.

Execution Table

Step	Signal/Variable	Value	Action	Result
1	A	4'b0011	Input set	A=3
2	B	4'b0101	Input set	B=5
3	Adder sum	4'b1000	Add A+B	3+5=8
4	LogicUnit logic_out	4'b0110	XOR A ^ B	3 ^ 5=6
5	Shifter shift_out	4'b0110	Shift A left by 1	3<<1=6
6	Op	2'b00	Select Adder output	Result=8
7	Result	4'b1000	Output assigned	Result=8
8	Op	2'b01	Select LogicUnit output	Result=6
9	Result	4'b0110	Output assigned	Result=6
10	Op	2'b10	Select Shifter output	Result=6
11	Result	4'b0110	Output assigned	Result=6
12	Op	2'b11	Default case	Result=0
13	Result	4'b0000	Output assigned	Result=0

💡 All Op cases tested; ALU outputs selected accordingly.

Variable Tracker

Variable	Start	After Step 3	After Step 4	After Step 5	Final
A	4'b0011	4'b0011	4'b0011	4'b0011	4'b0011
B	4'b0101	4'b0101	4'b0101	4'b0101	4'b0101
sum	undefined	4'b1000	4'b1000	4'b1000	4'b1000
logic_out	undefined	undefined	4'b0110	4'b0110	4'b0110
shift_out	undefined	undefined	undefined	4'b0110	4'b0110
Result	undefined	undefined	undefined	undefined	varies by Op

Key Moments - 3 Insights

Why does the ALU use submodules like Adder and LogicUnit instead of one big module?

Using submodules breaks the design into smaller parts, making it easier to build and test each function separately, as shown in the execution_table where each submodule produces its output independently.

How does the ALU decide which submodule output to use?

The ALU uses the Op input in a case statement (see steps 6, 8, 10 in execution_table) to select the correct output from the submodules.

What happens if Op has an unexpected value?

The default case sets Result to zero (step 12-13), ensuring the ALU output is always defined.

Visual Quiz - 3 Questions

Look at the execution_table at step 3, what is the value of 'sum'?

A 4'b0110

B 4'b1000

C 4'b0011

D 4'b0000

💡 Hint

Check the 'Value' column at step 3 in execution_table.

At which step does the ALU output the LogicUnit result?

A Step 6

B Step 10

C Step 8

D Step 12

💡 Hint

Look for when Op is 2'b01 in execution_table.

If Op is set to 2'b11, what will the Result be according to the execution_table?

A 4'b0000

B 4'b1000

C 4'b0110

D Undefined

💡 Hint

See the default case at steps 12 and 13 in execution_table.

Concept Snapshot

Design hierarchy for ALU in Verilog:
- Top module connects submodules (Adder, LogicUnit, Shifter)
- Inputs A, B and Op select operation
- Use 'case' to choose output
- Submodules compute independently
- Default output handles unexpected Op
- Modular design simplifies testing and reuse

Full Transcript

This visual execution shows how an ALU is designed using hierarchy in Verilog. The top ALU module connects smaller modules: Adder, LogicUnit, and Shifter. Inputs A and B are given, and Op selects which operation to output. Each submodule computes its result independently. The ALU uses a case statement to assign the final Result based on Op. If Op is unknown, Result defaults to zero. The execution table traces inputs, submodule outputs, and final Result for each Op value. Variable tracking shows how signals change step-by-step. Key moments clarify why modular design is used and how selection works. The quiz tests understanding of values at specific steps and default behavior.

Practice

1. What is the main benefit of using a design hierarchy when creating an ALU in Verilog?

easy

A. It removes the need for a top module to connect parts.

B. It makes the ALU run faster without changing the design.

C. It automatically generates testbenches for the ALU.

D. It breaks the ALU into smaller, manageable modules like adders and logic units.

Solution

1. Step 1: Understand design hierarchy concept

   Design hierarchy means dividing a big design into smaller modules for clarity and easier management.

2. Step 2: Apply to ALU design

   Breaking ALU into smaller parts like adders and logic units helps in understanding and fixing the design easily.

3. Final Answer:

   It breaks the ALU into smaller, manageable modules like adders and logic units. -> Option D

4. Quick Check:

   Design hierarchy = smaller modules [OK]

Hint: Think modular: big design = small parts [OK]

Common Mistakes:

• Assuming hierarchy speeds up ALU automatically
• Thinking top module is unnecessary
• Believing hierarchy creates testbenches

2. Which of the following is the correct way to instantiate a 4-bit adder module named adder4 inside a top ALU module in Verilog?

easy

A. adder4 add(.a(a), .b(b), .sum(sum));

B. adder4(a, b, sum);

C. adder4 add = (a, b, sum);

D. adder4 add {a, b, sum};

Solution

1. Step 1: Recall Verilog module instantiation syntax

   Correct syntax uses module name, instance name, and port connections with dot notation and parentheses.

2. Step 2: Check each option

   adder4 add(.a(a), .b(b), .sum(sum)); uses correct dot notation and parentheses. Options B, C, D have syntax errors or wrong format.

3. Final Answer:

   adder4 add(.a(a), .b(b), .sum(sum)); -> Option A

4. Quick Check:

   Correct instantiation = dot notation [OK]

Hint: Use dot and parentheses for ports [OK]

Common Mistakes:

• Omitting dot before port names
• Using equals sign instead of parentheses
• Using braces instead of parentheses

3. Given the following Verilog code snippet for a top ALU module, what will be the output result when op = 2'b01, a = 4'b0011, and b = 4'b0101?

module alu_top(input [3:0] a, b, input [1:0] op, output reg [3:0] result);
  wire [3:0] sum, and_out;
  adder4 add(.a(a), .b(b), .sum(sum));
  logic_unit logicu(.a(a), .b(b), .and_out(and_out));
  always @(*) begin
    case(op)
      2'b00: result = sum;
      2'b01: result = and_out;
      default: result = 4'b0000;
    endcase
  end
endmodule

medium

A. 4'b0110

B. 4'b0011

C. 4'b0001

D. 4'b0000

Solution

1. Step 1: Understand module connections and operations

   When op=2'b01, result is assigned from logic_unit output 'and_out', which is bitwise AND of a and b.

2. Step 2: Calculate bitwise AND of a=0011 and b=0101

   0011 AND 0101 = 0001 in binary.

3. Final Answer:

   4'b0001 -> Option C

4. Quick Check:

   Bitwise AND(0011,0101) = 0001 [OK]

Hint: Match op code to output source [OK]

Common Mistakes:

• Confusing sum with and_out
• Calculating OR instead of AND
• Ignoring op code in case statement

4. Identify the error in this Verilog top module instantiation of submodules for an ALU:

module alu_top(input [3:0] a, b, input [1:0] op, output reg [3:0] result);
  wire [3:0] sum, and_out;
  adder4 add(a, b, .sum(sum));
  logic_unit logicu(.a(a), .b(b), .and_out(and_out));
  always @(*) begin
    case(op)
      2'b00: result = sum;
      2'b01: result = and_out;
      default: result = 4'b0000;
    endcase
  end
endmodule

medium

A. Missing dot notation in adder4 instantiation causes syntax error.

B. logic_unit ports are incorrectly connected.

C. The always block should be replaced with an initial block.

D. The output 'result' should be a wire, not reg.

Solution

1. Step 1: Check module instantiations for syntax

   Adder4 instantiation uses positional ports without dot notation, which is allowed only if order matches exactly and ports are declared in module. But best practice and safer is dot notation.

2. Step 2: Identify error in given code

   Since logic_unit uses dot notation and adder4 does not, and if adder4 module expects named ports, missing dot notation causes syntax or connection error.

3. Final Answer:

   Missing dot notation in adder4 instantiation causes syntax error. -> Option A

4. Quick Check:

   Use dot notation for clarity and correctness [OK]

Hint: Use dot notation for all module ports [OK]

Common Mistakes:

• Thinking initial block is needed for combinational logic
• Changing reg to wire incorrectly
• Ignoring port connection style consistency

5. You want to extend your ALU design hierarchy by adding a subtractor module sub4 alongside the existing adder4 and logic_unit. How should you modify the top ALU module to select between addition and subtraction based on op signal, assuming op=2'b10 means subtraction?

hard

A. Replace adder4 with sub4 and ignore op=2'b10 case.

B. Instantiate sub4 module and add a case for 2'b10 to assign its output to result.

C. Add subtraction logic inside adder4 without new module.

D. Use a separate top module for subtraction and call it only when op=2'b10.

Solution

1. Step 1: Understand design hierarchy extension

   Adding a new subtractor module means instantiating it in the top module alongside existing modules.

2. Step 2: Modify case statement for op signal

   Add a case for op=2'b10 to assign the subtractor output to result, enabling selection between add and subtract.

3. Final Answer:

   Instantiate sub4 module and add a case for 2'b10 to assign its output to result. -> Option B

4. Quick Check:

   New module + case for op = extend hierarchy [OK]

Hint: Add module and case for new operation [OK]

Common Mistakes:

• Replacing adder instead of adding subtractor
• Ignoring op code for subtraction
• Creating separate top module unnecessarily