Design hierarchy for ALU in Verilog - Mini Project: Build & Apply

Design hierarchy for ALU

📖 Scenario: You are designing a simple Arithmetic Logic Unit (ALU) for a small processor. The ALU will perform basic operations like addition, subtraction, AND, and OR. To keep your design clean and easy to manage, you will use hierarchy by creating smaller modules and then combining them into a top-level ALU module.

🎯 Goal: Build a hierarchical Verilog design for an ALU by creating separate modules for addition and logic operations, then combine them in a top-level ALU module that selects the operation based on a control signal.

📋 What You'll Learn

Create a module called adder that adds two 4-bit inputs.

Create a module called logic_unit that performs AND and OR on two 4-bit inputs.

Create a top-level module called alu that uses adder and logic_unit modules.

Use a 2-bit control input op in alu to select the operation: 00 for addition, 01 for subtraction, 10 for AND, 11 for OR.

Output the 4-bit result from the selected operation.

💡 Why This Matters

🌍 Real World

Hierarchical design is used in real hardware projects to keep complex circuits organized and reusable.

💼 Career

Understanding module hierarchy and testbenches is essential for hardware engineers working on digital circuit design and verification.

1

Create the adder module

Write a Verilog module called adder that has two 4-bit inputs named a and b, and one 4-bit output named sum. The module should assign sum as the addition of a and b.

Verilog

module adder(input [3:0] a, input [3:0] b, output [3:0] sum);
    // Your code here
endmodule

Hint

Use assign sum = a + b; inside the module.

2

Create the logic_unit module

Write a Verilog module called logic_unit that has two 4-bit inputs named a and b, and two 4-bit outputs named and_out and or_out. The module should assign and_out as bitwise AND of a and b, and or_out as bitwise OR of a and b.

Verilog

module adder(input [3:0] a, input [3:0] b, output [3:0] sum);
    assign sum = a + b;
endmodule

module logic_unit(input [3:0] a, input [3:0] b, output [3:0] and_out, output [3:0] or_out);
    // Your code here
endmodule

Hint

Use assign and_out = a & b; and assign or_out = a | b;.

3

Create the top-level alu module

Write a Verilog module called alu with two 4-bit inputs a and b, a 2-bit input op, and one 4-bit output result. Instantiate the adder and logic_unit modules inside alu. Use a case statement on op to assign result: 2'b00 for addition, 2'b01 for subtraction (a - b), 2'b10 for AND, and 2'b11 for OR.

Verilog

module adder(input [3:0] a, input [3:0] b, output [3:0] sum);
    assign sum = a + b;
endmodule

module logic_unit(input [3:0] a, input [3:0] b, output [3:0] and_out, output [3:0] or_out);
    assign and_out = a & b;
    assign or_out = a | b;
endmodule

module alu(input [3:0] a, input [3:0] b, input [1:0] op, output reg [3:0] result);
    // Your code here
endmodule

Hint

Instantiate the modules and use a case statement inside an always @(*) block to select the output.

4

Test and display the ALU output

Write a testbench module called test_alu that declares a, b, and op as registers, and result as wire. Instantiate the alu module. Assign a = 4'b0101, b = 4'b0011. For each op value from 2'b00 to 2'b11, display the operation and the result using $display. Run the testbench to show the ALU output for all operations.

Verilog

module adder(input [3:0] a, input [3:0] b, output [3:0] sum);
    assign sum = a + b;
endmodule

module logic_unit(input [3:0] a, input [3:0] b, output [3:0] and_out, output [3:0] or_out);
    assign and_out = a & b;
    assign or_out = a | b;
endmodule

module alu(input [3:0] a, input [3:0] b, input [1:0] op, output reg [3:0] result);
    wire [3:0] sum;
    wire [3:0] and_out;
    wire [3:0] or_out;

    adder add_inst(.a(a), .b(b), .sum(sum));
    logic_unit logic_inst(.a(a), .b(b), .and_out(and_out), .or_out(or_out));

    always @(*) begin
        case(op)
            2'b00: result = sum;
            2'b01: result = a - b;
            2'b10: result = and_out;
            2'b11: result = or_out;
            default: result = 4'b0000;
        endcase
    end
endmodule

module test_alu;
    // Your code here
endmodule

Hint

Use a for loop to test all op values and $display to print results.

Practice

1. What is the main benefit of using a design hierarchy when creating an ALU in Verilog?

easy

A. It removes the need for a top module to connect parts.

B. It makes the ALU run faster without changing the design.

C. It automatically generates testbenches for the ALU.

D. It breaks the ALU into smaller, manageable modules like adders and logic units.

Solution

1. Step 1: Understand design hierarchy concept

   Design hierarchy means dividing a big design into smaller modules for clarity and easier management.

2. Step 2: Apply to ALU design

   Breaking ALU into smaller parts like adders and logic units helps in understanding and fixing the design easily.

3. Final Answer:

   It breaks the ALU into smaller, manageable modules like adders and logic units. -> Option D

4. Quick Check:

   Design hierarchy = smaller modules [OK]

Hint: Think modular: big design = small parts [OK]

Common Mistakes:

• Assuming hierarchy speeds up ALU automatically
• Thinking top module is unnecessary
• Believing hierarchy creates testbenches

2. Which of the following is the correct way to instantiate a 4-bit adder module named adder4 inside a top ALU module in Verilog?

easy

A. adder4 add(.a(a), .b(b), .sum(sum));

B. adder4(a, b, sum);

C. adder4 add = (a, b, sum);

D. adder4 add {a, b, sum};

Solution

1. Step 1: Recall Verilog module instantiation syntax

   Correct syntax uses module name, instance name, and port connections with dot notation and parentheses.

2. Step 2: Check each option

   adder4 add(.a(a), .b(b), .sum(sum)); uses correct dot notation and parentheses. Options B, C, D have syntax errors or wrong format.

3. Final Answer:

   adder4 add(.a(a), .b(b), .sum(sum)); -> Option A

4. Quick Check:

   Correct instantiation = dot notation [OK]

Hint: Use dot and parentheses for ports [OK]

Common Mistakes:

• Omitting dot before port names
• Using equals sign instead of parentheses
• Using braces instead of parentheses

3. Given the following Verilog code snippet for a top ALU module, what will be the output result when op = 2'b01, a = 4'b0011, and b = 4'b0101?

module alu_top(input [3:0] a, b, input [1:0] op, output reg [3:0] result);
  wire [3:0] sum, and_out;
  adder4 add(.a(a), .b(b), .sum(sum));
  logic_unit logicu(.a(a), .b(b), .and_out(and_out));
  always @(*) begin
    case(op)
      2'b00: result = sum;
      2'b01: result = and_out;
      default: result = 4'b0000;
    endcase
  end
endmodule

medium

A. 4'b0110

B. 4'b0011

C. 4'b0001

D. 4'b0000

Solution

1. Step 1: Understand module connections and operations

   When op=2'b01, result is assigned from logic_unit output 'and_out', which is bitwise AND of a and b.

2. Step 2: Calculate bitwise AND of a=0011 and b=0101

   0011 AND 0101 = 0001 in binary.

3. Final Answer:

   4'b0001 -> Option C

4. Quick Check:

   Bitwise AND(0011,0101) = 0001 [OK]

Hint: Match op code to output source [OK]

Common Mistakes:

• Confusing sum with and_out
• Calculating OR instead of AND
• Ignoring op code in case statement

4. Identify the error in this Verilog top module instantiation of submodules for an ALU:

module alu_top(input [3:0] a, b, input [1:0] op, output reg [3:0] result);
  wire [3:0] sum, and_out;
  adder4 add(a, b, .sum(sum));
  logic_unit logicu(.a(a), .b(b), .and_out(and_out));
  always @(*) begin
    case(op)
      2'b00: result = sum;
      2'b01: result = and_out;
      default: result = 4'b0000;
    endcase
  end
endmodule

medium

A. Missing dot notation in adder4 instantiation causes syntax error.

B. logic_unit ports are incorrectly connected.

C. The always block should be replaced with an initial block.

D. The output 'result' should be a wire, not reg.

Solution

1. Step 1: Check module instantiations for syntax

   Adder4 instantiation uses positional ports without dot notation, which is allowed only if order matches exactly and ports are declared in module. But best practice and safer is dot notation.

2. Step 2: Identify error in given code

   Since logic_unit uses dot notation and adder4 does not, and if adder4 module expects named ports, missing dot notation causes syntax or connection error.

3. Final Answer:

   Missing dot notation in adder4 instantiation causes syntax error. -> Option A

4. Quick Check:

   Use dot notation for clarity and correctness [OK]

Hint: Use dot notation for all module ports [OK]

Common Mistakes:

• Thinking initial block is needed for combinational logic
• Changing reg to wire incorrectly
• Ignoring port connection style consistency

5. You want to extend your ALU design hierarchy by adding a subtractor module sub4 alongside the existing adder4 and logic_unit. How should you modify the top ALU module to select between addition and subtraction based on op signal, assuming op=2'b10 means subtraction?

hard

A. Replace adder4 with sub4 and ignore op=2'b10 case.

B. Instantiate sub4 module and add a case for 2'b10 to assign its output to result.

C. Add subtraction logic inside adder4 without new module.

D. Use a separate top module for subtraction and call it only when op=2'b10.

Solution

1. Step 1: Understand design hierarchy extension

   Adding a new subtractor module means instantiating it in the top module alongside existing modules.

2. Step 2: Modify case statement for op signal

   Add a case for op=2'b10 to assign the subtractor output to result, enabling selection between add and subtract.

3. Final Answer:

   Instantiate sub4 module and add a case for 2'b10 to assign its output to result. -> Option B

4. Quick Check:

   New module + case for op = extend hierarchy [OK]

Hint: Add module and case for new operation [OK]

Common Mistakes:

• Replacing adder instead of adding subtractor
• Ignoring op code for subtraction
• Creating separate top module unnecessarily