Design hierarchy for ALU in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this ALU module for input A=4, B=3, and ALUop=2?

Consider this Verilog ALU module snippet. The ALUop controls the operation: 0=add, 1=subtract, 2=AND, 3=OR.

module ALU(input [3:0] A, input [3:0] B, input [1:0] ALUop, output reg [3:0] Result);
  always @(*) begin
    case (ALUop)
      2'b00: Result = A + B;
      2'b01: Result = A - B;
      2'b10: Result = A & B;
      2'b11: Result = A | B;
      default: Result = 4'b0000;
    endcase
  end
endmodule

What is the value of Result when A=4, B=3, ALUop=2?

Verilog

module ALU(input [3:0] A, input [3:0] B, input [1:0] ALUop, output reg [3:0] Result);
  always @(*) begin
    case (ALUop)
      2'b00: Result = A + B;
      2'b01: Result = A - B;
      2'b10: Result = A & B;
      2'b11: Result = A | B;
      default: Result = 4'b0000;
    endcase
  end
endmodule

A Result = 0 (4'b0000

B )0000b'4( 0 = tluseR

C esult = 0 (4'b0000)

D Result = 0 (4'b0000)

💡 Hint

Remember that ALUop=2 means AND operation between A and B.

ALUop=2 corresponds to bitwise AND. 4 (0100) & 3 (0011) = 0000 (decimal 0).

❓ Predict Output

intermediate

What is the output of this Verilog ALU hierarchy testbench?

Given the following testbench for a hierarchical ALU design, what is the printed output?

module ALU(input [3:0] A, input [3:0] B, input [1:0] ALUop, output reg [3:0] Result);
  always @(*) begin
    case (ALUop)
      2'b00: Result = A + B;
      2'b01: Result = A - B;
      2'b10: Result = A & B;
      2'b11: Result = A | B;
      default: Result = 4'b0000;
    endcase
  end
endmodule

module ALU_top();
  reg [3:0] A, B;
  reg [1:0] ALUop;
  wire [3:0] Result;
  ALU alu_inst(A, B, ALUop, Result);
  initial begin
    A = 4; B = 1; ALUop = 2'b01;
    #10;
    $display("Result = %d", Result);
  end
endmodule

Verilog

module ALU(input [3:0] A, input [3:0] B, input [1:0] ALUop, output reg [3:0] Result);
  always @(*) begin
    case (ALUop)
      2'b00: Result = A + B;
      2'b01: Result = A - B;
      2'b10: Result = A & B;
      2'b11: Result = A | B;
      default: Result = 4'b0000;
    endcase
  end
endmodule

module ALU_top();
  reg [3:0] A, B;
  reg [1:0] ALUop;
  wire [3:0] Result;
  ALU alu_inst(A, B, ALUop, Result);
  initial begin
    A = 4; B = 1; ALUop = 2'b01;
    #10;
    $display("Result = %d", Result);
  end
endmodule

A Result = 3

B Result = 1

C Result = 0

D Result = 5

💡 Hint

ALUop=01 means subtraction: A - B.

With A=4 and B=1, subtraction gives 3.

🔧 Debug

advanced

What error does this Verilog ALU hierarchy code produce?

Examine this Verilog code snippet for an ALU hierarchy. What error will the compiler report?

module ALU(input [3:0] A, input [3:0] B, input [1:0] ALUop, output reg [3:0] Result);
  always @(*) begin
    case ALUop
      2'b00: Result = A + B;
      2'b01: Result = A - B;
      2'b10: Result = A & B;
      2'b11: Result = A | B;
      default: Result = 4'b0000;
    endcase
  end
endmodule

Verilog

module ALU(input [3:0] A, input [3:0] B, input [1:0] ALUop, output reg [3:0] Result);
  always @(*) begin
    case ALUop
      2'b00: Result = A + B;
      2'b01: Result = A - B;
      2'b10: Result = A & B;
      2'b11: Result = A | B;
      default: Result = 4'b0000;
    endcase
  end
endmodule

A SyntaxError: Missing parentheses after 'case'

B SyntaxError: Missing colon after 'case ALUop'

C SyntaxError: Missing parentheses around ALUop in case statement

D No error, code compiles fine

💡 Hint

Check the syntax of the case statement in Verilog.

In Verilog, the case statement requires parentheses around the expression: case(ALUop).

🧠 Conceptual

advanced

How many modules are instantiated in this ALU hierarchy?

Given this Verilog hierarchy:

module Adder(input [3:0] A, input [3:0] B, output [3:0] Sum);
  assign Sum = A + B;
endmodule

module ALU(input [3:0] A, input [3:0] B, input [1:0] ALUop, output reg [3:0] Result);
  wire [3:0] sum_out;
  Adder add1(A, B, sum_out);
  always @(*) begin
    case(ALUop)
      2'b00: Result = sum_out;
      2'b01: Result = A - B;
      2'b10: Result = A & B;
      2'b11: Result = A | B;
      default: Result = 4'b0000;
    endcase
  end
endmodule

How many modules are instantiated inside the ALU module?

A 2

B 1

C 0

D 3

💡 Hint

Look for module instantiations inside ALU.

Only one module, Adder, is instantiated inside ALU.

🚀 Application

expert

What is the output of this hierarchical ALU with nested modules?

Consider this Verilog code with nested modules:

module AndGate(input [3:0] A, input [3:0] B, output [3:0] Out);
  assign Out = A & B;
endmodule

module OrGate(input [3:0] A, input [3:0] B, output [3:0] Out);
  assign Out = A | B;
endmodule

module ALU(input [3:0] A, input [3:0] B, input [1:0] ALUop, output reg [3:0] Result);
  wire [3:0] and_out, or_out;
  AndGate and1(A, B, and_out);
  OrGate or1(A, B, or_out);
  always @(*) begin
    case(ALUop)
      2'b10: Result = and_out;
      2'b11: Result = or_out;
      default: Result = 4'b1111;
    endcase
  end
endmodule

module ALU_top();
  reg [3:0] A, B;
  reg [1:0] ALUop;
  wire [3:0] Result;
  ALU alu_inst(A, B, ALUop, Result);
  initial begin
    A = 4'b1100; B = 4'b1010; ALUop = 2'b11;
    #10;
    $display("Result = %b", Result);
  end
endmodule

What is the printed Result?

Verilog

module AndGate(input [3:0] A, input [3:0] B, output [3:0] Out);
  assign Out = A & B;
endmodule

module OrGate(input [3:0] A, input [3:0] B, output [3:0] Out);
  assign Out = A | B;
endmodule

module ALU(input [3:0] A, input [3:0] B, input [1:0] ALUop, output reg [3:0] Result);
  wire [3:0] and_out, or_out;
  AndGate and1(A, B, and_out);
  OrGate or1(A, B, or_out);
  always @(*) begin
    case(ALUop)
      2'b10: Result = and_out;
      2'b11: Result = or_out;
      default: Result = 4'b1111;
    endcase
  end
endmodule

module ALU_top();
  reg [3:0] A, B;
  reg [1:0] ALUop;
  wire [3:0] Result;
  ALU alu_inst(A, B, ALUop, Result);
  initial begin
    A = 4'b1100; B = 4'b1010; ALUop = 2'b11;
    #10;
    $display("Result = %b", Result);
  end
endmodule

A Result = 1110

B Result = 1000

C Result = 1010

D Result = 1100

💡 Hint

ALUop=11 means OR operation between A and B.

Bitwise OR of 1100 and 1010 is 1110.

Practice

1. What is the main benefit of using a design hierarchy when creating an ALU in Verilog?

easy

A. It removes the need for a top module to connect parts.

B. It makes the ALU run faster without changing the design.

C. It automatically generates testbenches for the ALU.

D. It breaks the ALU into smaller, manageable modules like adders and logic units.

Solution

1. Step 1: Understand design hierarchy concept

   Design hierarchy means dividing a big design into smaller modules for clarity and easier management.

2. Step 2: Apply to ALU design

   Breaking ALU into smaller parts like adders and logic units helps in understanding and fixing the design easily.

3. Final Answer:

   It breaks the ALU into smaller, manageable modules like adders and logic units. -> Option D

4. Quick Check:

   Design hierarchy = smaller modules [OK]

Hint: Think modular: big design = small parts [OK]

Common Mistakes:

• Assuming hierarchy speeds up ALU automatically
• Thinking top module is unnecessary
• Believing hierarchy creates testbenches

2. Which of the following is the correct way to instantiate a 4-bit adder module named adder4 inside a top ALU module in Verilog?

easy

A. adder4 add(.a(a), .b(b), .sum(sum));

B. adder4(a, b, sum);

C. adder4 add = (a, b, sum);

D. adder4 add {a, b, sum};

Solution

1. Step 1: Recall Verilog module instantiation syntax

   Correct syntax uses module name, instance name, and port connections with dot notation and parentheses.

2. Step 2: Check each option

   adder4 add(.a(a), .b(b), .sum(sum)); uses correct dot notation and parentheses. Options B, C, D have syntax errors or wrong format.

3. Final Answer:

   adder4 add(.a(a), .b(b), .sum(sum)); -> Option A

4. Quick Check:

   Correct instantiation = dot notation [OK]

Hint: Use dot and parentheses for ports [OK]

Common Mistakes:

• Omitting dot before port names
• Using equals sign instead of parentheses
• Using braces instead of parentheses

3. Given the following Verilog code snippet for a top ALU module, what will be the output result when op = 2'b01, a = 4'b0011, and b = 4'b0101?

module alu_top(input [3:0] a, b, input [1:0] op, output reg [3:0] result);
  wire [3:0] sum, and_out;
  adder4 add(.a(a), .b(b), .sum(sum));
  logic_unit logicu(.a(a), .b(b), .and_out(and_out));
  always @(*) begin
    case(op)
      2'b00: result = sum;
      2'b01: result = and_out;
      default: result = 4'b0000;
    endcase
  end
endmodule

medium

A. 4'b0110

B. 4'b0011

C. 4'b0001

D. 4'b0000

Solution

1. Step 1: Understand module connections and operations

   When op=2'b01, result is assigned from logic_unit output 'and_out', which is bitwise AND of a and b.

2. Step 2: Calculate bitwise AND of a=0011 and b=0101

   0011 AND 0101 = 0001 in binary.

3. Final Answer:

   4'b0001 -> Option C

4. Quick Check:

   Bitwise AND(0011,0101) = 0001 [OK]

Hint: Match op code to output source [OK]

Common Mistakes:

• Confusing sum with and_out
• Calculating OR instead of AND
• Ignoring op code in case statement

4. Identify the error in this Verilog top module instantiation of submodules for an ALU:

module alu_top(input [3:0] a, b, input [1:0] op, output reg [3:0] result);
  wire [3:0] sum, and_out;
  adder4 add(a, b, .sum(sum));
  logic_unit logicu(.a(a), .b(b), .and_out(and_out));
  always @(*) begin
    case(op)
      2'b00: result = sum;
      2'b01: result = and_out;
      default: result = 4'b0000;
    endcase
  end
endmodule

medium

A. Missing dot notation in adder4 instantiation causes syntax error.

B. logic_unit ports are incorrectly connected.

C. The always block should be replaced with an initial block.

D. The output 'result' should be a wire, not reg.

Solution

1. Step 1: Check module instantiations for syntax

   Adder4 instantiation uses positional ports without dot notation, which is allowed only if order matches exactly and ports are declared in module. But best practice and safer is dot notation.

2. Step 2: Identify error in given code

   Since logic_unit uses dot notation and adder4 does not, and if adder4 module expects named ports, missing dot notation causes syntax or connection error.

3. Final Answer:

   Missing dot notation in adder4 instantiation causes syntax error. -> Option A

4. Quick Check:

   Use dot notation for clarity and correctness [OK]

Hint: Use dot notation for all module ports [OK]

Common Mistakes:

• Thinking initial block is needed for combinational logic
• Changing reg to wire incorrectly
• Ignoring port connection style consistency

5. You want to extend your ALU design hierarchy by adding a subtractor module sub4 alongside the existing adder4 and logic_unit. How should you modify the top ALU module to select between addition and subtraction based on op signal, assuming op=2'b10 means subtraction?

hard

A. Replace adder4 with sub4 and ignore op=2'b10 case.

B. Instantiate sub4 module and add a case for 2'b10 to assign its output to result.

C. Add subtraction logic inside adder4 without new module.

D. Use a separate top module for subtraction and call it only when op=2'b10.

Solution

1. Step 1: Understand design hierarchy extension

   Adding a new subtractor module means instantiating it in the top module alongside existing modules.

2. Step 2: Modify case statement for op signal

   Add a case for op=2'b10 to assign the subtractor output to result, enabling selection between add and subtract.

3. Final Answer:

   Instantiate sub4 module and add a case for 2'b10 to assign its output to result. -> Option B

4. Quick Check:

   New module + case for op = extend hierarchy [OK]

Hint: Add module and case for new operation [OK]

Common Mistakes:

• Replacing adder instead of adding subtractor
• Ignoring op code for subtraction
• Creating separate top module unnecessarily