Critical path and timing closure in Verilog - Step-by-Step Execution

Concept Flow - Critical path and timing closure

Design RTL Code

↓

Synthesis: Map to gates

↓

Static Timing Analysis

↓

Identify Critical Path

↓

Optimize Design (e.g., pipeline, buffer)

↓

Re-run Timing Analysis

↓

Timing Met?

No→Further Optimization

↓

Timing Closure Achieved

The flow shows how a Verilog design is synthesized, analyzed for timing, optimized to fix critical paths, and iterated until timing closure is achieved.

Execution Sample

Verilog

module simple_pipe(input clk, input a, output reg y);
  reg q1, q2;
  always @(posedge clk) begin
    q1 <= a;
    q2 <= q1;
    y <= q2;
  end
endmodule

A simple 3-stage pipeline registers input 'a' to output 'y' on clock edges to improve timing.

Execution Table

Step	Action	Critical Path Delay (ns)	Timing Met?	Next Step
1	Initial synthesis	12.5	No	Optimize pipeline stages
2	Add pipeline registers	7.8	No	Add buffers and retime
3	Insert buffers	5.2	Yes	Timing closure achieved

💡 Timing closure achieved when critical path delay is less than clock period.

Variable Tracker

Variable	Start	After Step 1	After Step 2	Final
Critical Path Delay (ns)	N/A	12.5	7.8	5.2
Timing Met?	N/A	No	No	Yes

Key Moments - 3 Insights

Why does adding pipeline registers reduce the critical path delay?

Adding pipeline registers breaks a long combinational path into shorter stages, reducing delay per stage as shown between Step 1 and Step 2 in the execution_table.

What does 'Timing Met?' mean in the context of the critical path?

'Timing Met?' means the critical path delay is less than the clock period, so signals arrive on time. In the table, it changes from 'No' to 'Yes' at Step 3.

Why might buffers be added after pipelining?

Buffers help drive signals faster and reduce delay on long wires, further improving timing after pipelining, as seen from Step 2 to Step 3.

Visual Quiz - 3 Questions

Look at the execution_table, what is the critical path delay after adding pipeline registers?

A 12.5 ns

B 5.2 ns

C 7.8 ns

D N/A

💡 Hint

Check the 'Critical Path Delay (ns)' column at Step 2 in the execution_table.

At which step does the timing closure get achieved?

A Step 3

B Step 2

C Step 1

D Never

💡 Hint

Look at the 'Timing Met?' column in the execution_table to find when it changes to 'Yes'.

If the clock period was reduced, what would likely happen to the 'Timing Met?' status in the variable_tracker?

A It would stay Yes

B It would change from Yes to No

C It would become N/A

D It would change from No to Yes

💡 Hint

If clock period is shorter than critical path delay, timing is not met; see variable_tracker for timing status.

Concept Snapshot

Critical path is the longest delay path in a design.
Timing closure means all paths meet the clock period.
Add pipeline registers to split long paths.
Use buffers to speed signals.
Iterate synthesis and analysis until timing is met.

Full Transcript

This visual execution shows how a Verilog design goes through synthesis and timing analysis to find the critical path delay. Initially, the delay is too long, so pipeline registers are added to break the path into shorter stages, reducing delay. Then buffers are inserted to further speed signals. After these optimizations, timing closure is achieved when the critical path delay is less than the clock period. Variables like critical path delay and timing status are tracked step-by-step. Key moments explain why pipelining and buffering help timing. Quiz questions check understanding of delay changes and timing closure steps.

Practice

1. What is the critical path in a Verilog design?

easy

A. The shortest path between two registers

B. The slowest signal path that limits the maximum clock frequency

C. A path that has no timing constraints

D. The path with the most logic gates regardless of delay

Solution

1. Step 1: Understand critical path definition

   The critical path is the longest delay path in the design that determines the maximum speed.

2. Step 2: Identify the impact on clock frequency

   The slowest path limits how fast the clock can run without errors.

3. Final Answer:

   The slowest signal path that limits the maximum clock frequency -> Option B

4. Quick Check:

   Critical path = slowest path [OK]

Hint: Critical path = slowest path limiting clock speed [OK]

Common Mistakes:

• Confusing critical path with shortest path
• Ignoring timing constraints
• Thinking critical path is about number of gates

2. Which of the following is the correct way to specify a timing constraint in Verilog for a clock period of 10ns?

easy

A. `timescale 1ns / 1ps\n// No timing constraint specified here

B. // specify clock period\n$period(clock, 10);

C. specify\n specparam tCK = 10ns;\nendspecify

D. specify\n specparam tCK = 10;\nendspecify

Solution

1. Step 1: Understand timing constraint syntax

   In Verilog specify blocks, specparam defines timing parameters without units; units come from `timescale.

2. Step 2: Check correct usage of specparam

   specify\n specparam tCK = 10;\nendspecify correctly sets tCK = 10 (ns implied by timescale), inside specify block.

3. Final Answer:

   specify\n specparam tCK = 10;\nendspecify -> Option D

4. Quick Check:

   specparam with numeric value = correct timing constraint [OK]

Hint: Use specify block with specparam and numeric value [OK]

Common Mistakes:

• Using units inside specparam value
• Missing specify block
• Confusing timescale with timing constraints

3. Given the following Verilog code snippet, what is the critical path delay assuming gate delays are 2ns each?

module example(input clk, input a, b, output reg y);
  reg x;
  always @(posedge clk) begin
    x <= a & b;
    y <= x | b;
  end
endmodule

medium

A. 4 ns

B. 2 ns

C. 6 ns

D. 8 ns

Solution

1. Step 1: Identify combinational logic paths

   'a & b' (AND gate, 2ns) from inputs to x; 'x | b' (OR gate, 2ns) from x output and b to y.

2. Step 2: Determine longest path

   Non-blocking assignments (<=) update registers on clock edge, so delays add up through combinational logic between registers. Critical path is sum of both gates: 2ns + 2ns = 4ns.

3. Final Answer:

   4 ns -> Option A

4. Quick Check:

   Sum of gate delays in path = 4ns [OK]

Hint: Sum gate delays between registers for critical path [OK]

Common Mistakes:

• Adding unrelated gate delays
• Assuming chained logic with NBA
• Ignoring non-blocking semantics

4. Identify the timing closure issue in this Verilog snippet:

always @(posedge clk) begin
  reg1 <= input_signal;
  reg2 <= reg1 & control;
  reg3 <= reg2 | enable;
end

medium

A. No timing issue, all registers update correctly

B. Missing reset signal causes timing closure failure

C. Critical path is too long through reg1, reg2, and reg3 causing timing violation

D. Incorrect use of blocking assignments causing race conditions

Solution

1. Step 1: Analyze assignments with non-blocking operators

   reg2 <= reg1 & control uses prior reg1; reg3 <= reg2 | enable uses prior reg2.

2. Step 2: Identify combo paths

   reg1.q & control to reg2 (1 gate); reg2.q | enable to reg3 (1 gate); input to reg1 (0 gates). All short.

3. Final Answer:

   No timing issue, all registers update correctly -> Option A

4. Quick Check:

   Short paths with NBA = no violation [OK]

Hint: NBA keeps combo paths short in clocked always blocks [OK]

Common Mistakes:

• Mistaking NBA for blocking creating long paths
• Confusing functional update with timing paths
• Assuming reset affects timing closure

5. You have a critical path delay of 12ns but your clock period is 10ns. Which of the following is the best approach to achieve timing closure in your Verilog design?

hard

A. Increase the clock period to 15ns to meet timing

B. Replace all combinational logic with sequential logic

C. Add pipeline registers to break the critical path into shorter stages

D. Remove all timing constraints to let the tool optimize automatically

Solution

1. Step 1: Understand timing closure goal

   Timing closure means meeting the clock period by fixing critical paths.

2. Step 2: Evaluate options to reduce critical path delay

   Adding pipeline registers breaks long paths into shorter ones, reducing delay per stage.

3. Step 3: Reject other options

   Increasing clock period reduces performance, removing constraints is bad practice, replacing all logic is impractical.

4. Final Answer:

   Add pipeline registers to break the critical path into shorter stages -> Option C

5. Quick Check:

   Pipeline registers = timing closure technique [OK]

Hint: Use pipelining to split long critical paths [OK]

Common Mistakes:

• Ignoring performance impact of increasing clock period
• Removing timing constraints
• Misunderstanding logic types