Critical path and timing closure in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Identify the critical path delay in this Verilog module

Given the following Verilog code, what is the critical path delay assuming each gate has a delay of 1ns?

Verilog

module logic_path(input wire a, b, c, d, output wire y);
  wire w1, w2, w3;
  assign w1 = a & b;
  assign w2 = w1 | c;
  assign w3 = w2 ^ d;
  assign y = ~w3;
endmodule

A 3 ns

B 4 ns

C 5 ns

D 2 ns

💡 Hint

Count the number of gates in the longest path from input to output.

The longest path is a -> w1 (AND) -> w2 (OR) -> w3 (XOR) -> y (NOT), totaling 4 gates, each 1ns delay, so 4 ns total.

🧠 Conceptual

intermediate

What does timing closure mean in digital design?

Choose the best description of timing closure in the context of digital circuit design.

A Maximizing the number of logic gates in the design to increase complexity.

B Minimizing the power consumption of the circuit by reducing switching activity.

C Ensuring all signals meet their required timing constraints so the circuit works correctly at the target clock frequency.

D Writing testbenches to verify functional correctness of the design.

💡 Hint

Think about what 'closure' means in timing context.

Timing closure means the design meets all timing requirements so it can run reliably at the desired clock speed.

🔧 Debug

advanced

Find the timing violation in this Verilog snippet

Given the following code, which part is most likely causing a timing violation?

Verilog

module timing_violation(input clk, a, b, output reg y);
  reg w1, w2;
  always @(posedge clk) begin
    w1 <= a & b;
    w2 <= w1 | b;
    y <= w2 ^ a;
  end
endmodule

A The output y is assigned asynchronously outside the clock edge.

B The module is missing a reset signal.

C The inputs a and b are not declared as wires.

D The assignment to w2 depends on w1 which is updated in the same clock cycle, causing a timing violation.

💡 Hint

Consider how data flows between registers within one clock cycle.

Because w2 depends on w1 which is updated on the same clock edge, the logic between registers is combinational and may be too long, causing timing violation.

📝 Syntax

advanced

Which Verilog code correctly implements a pipeline stage to improve timing?

Select the code snippet that correctly adds a pipeline register stage to break a long combinational path.

A

always @(posedge clk) begin
  stage1 <= input_signal;
  stage2 <= stage1;
  output_signal <= stage2;
end

B

always @(posedge clk) begin
  stage1 = input_signal;
  stage2 = stage1;
  output_signal = stage2;
end

C

always @(input_signal) begin
  stage1 <= input_signal;
  stage2 <= stage1;
  output_signal <= stage2;
end

D

always @(posedge clk) begin
  stage1 <= input_signal;
  output_signal <= stage1;
  stage2 <= output_signal;
end

💡 Hint

Remember that non-blocking assignments (<=) are used in sequential logic triggered by clock edges.

Option A uses non-blocking assignments inside a clocked always block, correctly implementing pipeline registers.

🚀 Application

expert

Calculate the maximum clock frequency after timing optimization

A design has a critical path delay of 12 ns initially. After applying pipelining and logic optimization, the critical path delay is reduced to 4 ns. What is the maximum clock frequency achievable after optimization?

A 250 MHz

B 12 MHz

C 83.3 MHz

D 48 MHz

💡 Hint

Recall that frequency = 1 / period, and period is the critical path delay.

Maximum frequency = 1 / 4 ns = 250 MHz.

Practice

1. What is the critical path in a Verilog design?

easy

A. The shortest path between two registers

B. The slowest signal path that limits the maximum clock frequency

C. A path that has no timing constraints

D. The path with the most logic gates regardless of delay

Solution

1. Step 1: Understand critical path definition

   The critical path is the longest delay path in the design that determines the maximum speed.

2. Step 2: Identify the impact on clock frequency

   The slowest path limits how fast the clock can run without errors.

3. Final Answer:

   The slowest signal path that limits the maximum clock frequency -> Option B

4. Quick Check:

   Critical path = slowest path [OK]

Hint: Critical path = slowest path limiting clock speed [OK]

Common Mistakes:

• Confusing critical path with shortest path
• Ignoring timing constraints
• Thinking critical path is about number of gates

2. Which of the following is the correct way to specify a timing constraint in Verilog for a clock period of 10ns?

easy

A. `timescale 1ns / 1ps\n// No timing constraint specified here

B. // specify clock period\n$period(clock, 10);

C. specify\n specparam tCK = 10ns;\nendspecify

D. specify\n specparam tCK = 10;\nendspecify

Solution

1. Step 1: Understand timing constraint syntax

   In Verilog specify blocks, specparam defines timing parameters without units; units come from `timescale.

2. Step 2: Check correct usage of specparam

   specify\n specparam tCK = 10;\nendspecify correctly sets tCK = 10 (ns implied by timescale), inside specify block.

3. Final Answer:

   specify\n specparam tCK = 10;\nendspecify -> Option D

4. Quick Check:

   specparam with numeric value = correct timing constraint [OK]

Hint: Use specify block with specparam and numeric value [OK]

Common Mistakes:

• Using units inside specparam value
• Missing specify block
• Confusing timescale with timing constraints

3. Given the following Verilog code snippet, what is the critical path delay assuming gate delays are 2ns each?

module example(input clk, input a, b, output reg y);
  reg x;
  always @(posedge clk) begin
    x <= a & b;
    y <= x | b;
  end
endmodule

medium

A. 4 ns

B. 2 ns

C. 6 ns

D. 8 ns

Solution

1. Step 1: Identify combinational logic paths

   'a & b' (AND gate, 2ns) from inputs to x; 'x | b' (OR gate, 2ns) from x output and b to y.

2. Step 2: Determine longest path

   Non-blocking assignments (<=) update registers on clock edge, so delays add up through combinational logic between registers. Critical path is sum of both gates: 2ns + 2ns = 4ns.

3. Final Answer:

   4 ns -> Option A

4. Quick Check:

   Sum of gate delays in path = 4ns [OK]

Hint: Sum gate delays between registers for critical path [OK]

Common Mistakes:

• Adding unrelated gate delays
• Assuming chained logic with NBA
• Ignoring non-blocking semantics

4. Identify the timing closure issue in this Verilog snippet:

always @(posedge clk) begin
  reg1 <= input_signal;
  reg2 <= reg1 & control;
  reg3 <= reg2 | enable;
end

medium

A. No timing issue, all registers update correctly

B. Missing reset signal causes timing closure failure

C. Critical path is too long through reg1, reg2, and reg3 causing timing violation

D. Incorrect use of blocking assignments causing race conditions

Solution

1. Step 1: Analyze assignments with non-blocking operators

   reg2 <= reg1 & control uses prior reg1; reg3 <= reg2 | enable uses prior reg2.

2. Step 2: Identify combo paths

   reg1.q & control to reg2 (1 gate); reg2.q | enable to reg3 (1 gate); input to reg1 (0 gates). All short.

3. Final Answer:

   No timing issue, all registers update correctly -> Option A

4. Quick Check:

   Short paths with NBA = no violation [OK]

Hint: NBA keeps combo paths short in clocked always blocks [OK]

Common Mistakes:

• Mistaking NBA for blocking creating long paths
• Confusing functional update with timing paths
• Assuming reset affects timing closure

5. You have a critical path delay of 12ns but your clock period is 10ns. Which of the following is the best approach to achieve timing closure in your Verilog design?

hard

A. Increase the clock period to 15ns to meet timing

B. Replace all combinational logic with sequential logic

C. Add pipeline registers to break the critical path into shorter stages

D. Remove all timing constraints to let the tool optimize automatically

Solution

1. Step 1: Understand timing closure goal

   Timing closure means meeting the clock period by fixing critical paths.

2. Step 2: Evaluate options to reduce critical path delay

   Adding pipeline registers breaks long paths into shorter ones, reducing delay per stage.

3. Step 3: Reject other options

   Increasing clock period reduces performance, removing constraints is bad practice, replacing all logic is impractical.

4. Final Answer:

   Add pipeline registers to break the critical path into shorter stages -> Option C

5. Quick Check:

   Pipeline registers = timing closure technique [OK]

Hint: Use pipelining to split long critical paths [OK]

Common Mistakes:

• Ignoring performance impact of increasing clock period
• Removing timing constraints
• Misunderstanding logic types