Critical path and timing closure in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a clock signal in Verilog.

Verilog

reg [1];

Drag options to blanks, or click blank then click option'

Aclk

Breset

Cdata

Denable

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'reset' or 'enable' instead of 'clk' for the clock signal.

The clock signal is usually named clk and declared as a reg type in Verilog.

2fill in blank

medium

Complete the code to create a positive edge triggered always block.

Verilog

always @([1] clk) begin
  // logic here
end

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Aposedge

Bedge

Clevel

Dnegedge

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'negedge' which triggers on falling edge.

Using 'level' or 'edge' which are not valid keywords.

The posedge keyword triggers the block on the rising edge of the clock.

3fill in blank

hard

Fix the error in the code to correctly assign a value inside an always block.

Verilog

always @(posedge clk) begin
  [1] = data_in;
end

Drag options to blanks, or click blank then click option'

Awire_out

Breg_out

Cassign_out

Doutput_wire

Attempts:

3 left

💡 Hint

Common Mistakes

Trying to assign to a wire inside an always block causes errors.

Inside an always block, you must assign to a reg type variable, not a wire.

4fill in blank

hard

Fill both blanks to create a combinational always block sensitive to inputs a and b.

Verilog

always @([1] or [2]) begin
  out = a & b;
end

Drag options to blanks, or click blank then click option'

Aa

Bb

Cclk

Dreset

Attempts:

3 left

💡 Hint

Common Mistakes

Including clock or reset signals in combinational sensitivity list.

A combinational block should be sensitive to all inputs it uses, here a and b.

5fill in blank

hard

Fill all three blanks to create a timing constraint for a clock named clk with a period of 10ns.

Verilog

create_clock -name [1] -period [2] -waveform {0 [3]

Drag options to blanks, or click blank then click option'

Aclk

B10

C5

Dreset

Attempts:

3 left

💡 Hint

Common Mistakes

Using wrong clock name or incorrect waveform timing values.

The clock name is clk, period is 10ns, and waveform rising edge is at 0ns, falling edge at 5ns (half period).

Practice

1. What is the critical path in a Verilog design?

easy

A. The shortest path between two registers

B. The slowest signal path that limits the maximum clock frequency

C. A path that has no timing constraints

D. The path with the most logic gates regardless of delay

Solution

1. Step 1: Understand critical path definition

   The critical path is the longest delay path in the design that determines the maximum speed.

2. Step 2: Identify the impact on clock frequency

   The slowest path limits how fast the clock can run without errors.

3. Final Answer:

   The slowest signal path that limits the maximum clock frequency -> Option B

4. Quick Check:

   Critical path = slowest path [OK]

Hint: Critical path = slowest path limiting clock speed [OK]

Common Mistakes:

• Confusing critical path with shortest path
• Ignoring timing constraints
• Thinking critical path is about number of gates

2. Which of the following is the correct way to specify a timing constraint in Verilog for a clock period of 10ns?

easy

A. `timescale 1ns / 1ps\n// No timing constraint specified here

B. // specify clock period\n$period(clock, 10);

C. specify\n specparam tCK = 10ns;\nendspecify

D. specify\n specparam tCK = 10;\nendspecify

Solution

1. Step 1: Understand timing constraint syntax

   In Verilog specify blocks, specparam defines timing parameters without units; units come from `timescale.

2. Step 2: Check correct usage of specparam

   specify\n specparam tCK = 10;\nendspecify correctly sets tCK = 10 (ns implied by timescale), inside specify block.

3. Final Answer:

   specify\n specparam tCK = 10;\nendspecify -> Option D

4. Quick Check:

   specparam with numeric value = correct timing constraint [OK]

Hint: Use specify block with specparam and numeric value [OK]

Common Mistakes:

• Using units inside specparam value
• Missing specify block
• Confusing timescale with timing constraints

3. Given the following Verilog code snippet, what is the critical path delay assuming gate delays are 2ns each?

module example(input clk, input a, b, output reg y);
  reg x;
  always @(posedge clk) begin
    x <= a & b;
    y <= x | b;
  end
endmodule

medium

A. 4 ns

B. 2 ns

C. 6 ns

D. 8 ns

Solution

1. Step 1: Identify combinational logic paths

   'a & b' (AND gate, 2ns) from inputs to x; 'x | b' (OR gate, 2ns) from x output and b to y.

2. Step 2: Determine longest path

   Non-blocking assignments (<=) update registers on clock edge, so delays add up through combinational logic between registers. Critical path is sum of both gates: 2ns + 2ns = 4ns.

3. Final Answer:

   4 ns -> Option A

4. Quick Check:

   Sum of gate delays in path = 4ns [OK]

Hint: Sum gate delays between registers for critical path [OK]

Common Mistakes:

• Adding unrelated gate delays
• Assuming chained logic with NBA
• Ignoring non-blocking semantics

4. Identify the timing closure issue in this Verilog snippet:

always @(posedge clk) begin
  reg1 <= input_signal;
  reg2 <= reg1 & control;
  reg3 <= reg2 | enable;
end

medium

A. No timing issue, all registers update correctly

B. Missing reset signal causes timing closure failure

C. Critical path is too long through reg1, reg2, and reg3 causing timing violation

D. Incorrect use of blocking assignments causing race conditions

Solution

1. Step 1: Analyze assignments with non-blocking operators

   reg2 <= reg1 & control uses prior reg1; reg3 <= reg2 | enable uses prior reg2.

2. Step 2: Identify combo paths

   reg1.q & control to reg2 (1 gate); reg2.q | enable to reg3 (1 gate); input to reg1 (0 gates). All short.

3. Final Answer:

   No timing issue, all registers update correctly -> Option A

4. Quick Check:

   Short paths with NBA = no violation [OK]

Hint: NBA keeps combo paths short in clocked always blocks [OK]

Common Mistakes:

• Mistaking NBA for blocking creating long paths
• Confusing functional update with timing paths
• Assuming reset affects timing closure

5. You have a critical path delay of 12ns but your clock period is 10ns. Which of the following is the best approach to achieve timing closure in your Verilog design?

hard

A. Increase the clock period to 15ns to meet timing

B. Replace all combinational logic with sequential logic

C. Add pipeline registers to break the critical path into shorter stages

D. Remove all timing constraints to let the tool optimize automatically

Solution

1. Step 1: Understand timing closure goal

   Timing closure means meeting the clock period by fixing critical paths.

2. Step 2: Evaluate options to reduce critical path delay

   Adding pipeline registers breaks long paths into shorter ones, reducing delay per stage.

3. Step 3: Reject other options

   Increasing clock period reduces performance, removing constraints is bad practice, replacing all logic is impractical.

4. Final Answer:

   Add pipeline registers to break the critical path into shorter stages -> Option C

5. Quick Check:

   Pipeline registers = timing closure technique [OK]

Hint: Use pipelining to split long critical paths [OK]

Common Mistakes:

• Ignoring performance impact of increasing clock period
• Removing timing constraints
• Misunderstanding logic types