Clock gating for power reduction in Verilog - Step-by-Step Execution

Concept Flow - Clock gating for power reduction

Input Clock

↓

Enable Signal Check

↓

Pass Clock

↓

Flip-Flop or Logic Block

↓

Output Signal

The clock signal is passed or blocked based on an enable signal to reduce power by stopping unnecessary clock toggling.

Execution Sample

Verilog

module clock_gating(
  input clk,
  input enable,
  output gated_clk
);
  assign gated_clk = clk & enable;
endmodule

This simple clock gating module outputs the clock only when enable is high, reducing switching activity.

Execution Table

Step	clk	enable	gated_clk (clk & enable)	Action
1	0	0	0	Clock low, enable low, gated_clk low
2	1	0	0	Clock high, enable low, gated_clk blocked (0)
3	1	1	1	Clock high, enable high, gated_clk passes (1)
4	0	1	0	Clock low, enable high, gated_clk low
5	1	1	1	Clock high, enable high, gated_clk passes (1)
6	0	0	0	Clock low, enable low, gated_clk blocked (0)

💡 Simulation ends after 6 steps showing gated clock behavior with enable signal.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6
clk	0	0	1	1	0	1	0
enable	0	0	0	1	1	1	0
gated_clk	0	0	0	1	0	1	0

Key Moments - 3 Insights

Why is gated_clk zero when clk is high but enable is zero?

Because gated_clk is the AND of clk and enable (see execution_table step 2), if enable is zero, gated_clk blocks the clock to save power.

Does gated_clk toggle when enable is zero?

No, gated_clk stays low when enable is zero, even if clk toggles (execution_table steps 1,2,6). This stops unnecessary switching.

What happens to gated_clk when both clk and enable are high?

gated_clk follows clk and becomes high (execution_table steps 3 and 5), allowing the clock to reach downstream logic.

Visual Quiz - 3 Questions

Look at the execution_table, what is gated_clk at step 4 when clk=0 and enable=1?

A 0

B 1

C Undefined

D Same as clk

💡 Hint

Check the gated_clk column at step 4 in execution_table.

At which step does gated_clk first become 1?

A Step 2

B Step 3

C Step 1

D Step 6

💡 Hint

Look for the first row where gated_clk is 1 in execution_table.

If enable stayed always high, how would gated_clk behave?

A It would always be 0

B It would be always high

C It would follow clk exactly

D It would toggle randomly

💡 Hint

Refer to variable_tracker and execution_table where enable=1 and gated_clk matches clk.

Concept Snapshot

Clock gating reduces power by stopping clock toggling when not needed.
Use an enable signal to AND with the clock.
When enable=0, gated clock stops toggling.
When enable=1, clock passes through.
Simple AND gate can implement clock gating.
Helps save power in synchronous circuits.

Full Transcript

Clock gating is a technique to save power by controlling when the clock signal reaches parts of a circuit. The clock signal is combined with an enable signal using an AND gate. When enable is low, the gated clock stays low, preventing unnecessary switching and saving power. When enable is high, the gated clock follows the input clock, allowing normal operation. The example Verilog code shows a module that outputs gated_clk as clk AND enable. The execution table traces clk, enable, and gated_clk values step-by-step, showing how gated_clk changes only when enable is high. Key moments clarify why gated_clk blocks the clock when enable is zero and passes it when enable is one. The visual quiz tests understanding of gated_clk behavior at different steps. This technique is simple but effective for power reduction in digital designs.

Practice

1. What is the main purpose of clock gating in Verilog designs?

easy

A. To increase the clock frequency for faster operation

B. To reduce power consumption by disabling the clock to inactive modules

C. To add delay to the clock signal intentionally

D. To synchronize multiple clock domains

Solution

1. Step 1: Understand clock gating concept

   Clock gating is used to save power by stopping the clock signal to parts of the circuit that are not active.

2. Step 2: Identify the main goal

   The main goal is to reduce power consumption, not to increase speed or add delay.

3. Final Answer:

   To reduce power consumption by disabling the clock to inactive modules -> Option B

4. Quick Check:

   Clock gating = power saving [OK]

Hint: Clock gating stops clock to idle parts to save power [OK]

Common Mistakes:

• Thinking clock gating speeds up the circuit
• Confusing clock gating with clock synchronization
• Assuming clock gating adds intentional delay

2. Which of the following is the correct way to implement clock gating in Verilog?

easy

A. assign gated_clk = ~clk & enable;

B. assign gated_clk = clk | enable;

C. assign gated_clk = clk & enable;

D. assign gated_clk = clk ^ enable;

Solution

1. Step 1: Recall clock gating logic

   Clock gating is done by ANDing the clock with an enable signal to stop the clock when enable is low.

2. Step 2: Check each option

   Only assign gated_clk = clk & enable; uses AND (&) between clock and enable, which is correct for gating.

3. Final Answer:

   assign gated_clk = clk & enable; -> Option C

4. Quick Check:

   Clock gating = clk AND enable [OK]

Hint: Clock gating uses AND between clock and enable [OK]

Common Mistakes:

• Using OR or XOR instead of AND for gating
• Negating clock signal incorrectly
• Confusing enable signal polarity

3. Given the following Verilog snippet, what is the value of gated_clk when clk=1 and enable=0?

assign gated_clk = clk & enable;

medium

A. X (unknown)

B. 1

C. Z (high impedance)

D. 0

Solution

1. Step 1: Evaluate the AND operation

   gated_clk = clk & enable = 1 & 0 = 0.

2. Step 2: Understand output value

   Since enable is 0, gated_clk is forced to 0 regardless of clk.

3. Final Answer:

   0 -> Option D

4. Quick Check:

   1 AND 0 = 0 [OK]

Hint: AND with zero always gives zero [OK]

Common Mistakes:

• Assuming gated_clk equals clk regardless of enable
• Confusing zero with unknown or high impedance
• Thinking gated_clk is always 1 when clk is 1

4. Identify the error in this clock gating code snippet:

module clk_gate(input clk, input enable, output gated_clk);
  always @(posedge clk) begin
    if (enable)
      gated_clk <= clk;
    else
      gated_clk <= 0;
  end
endmodule

medium

A. Using gated_clk as a clock signal inside always block causes timing issues

B. Missing sensitivity to enable signal in always block

C. Incorrect use of nonblocking assignment for gated_clk

D. No error; code is correct

Solution

1. Step 1: Analyze clock gating implementation

   The code tries to assign gated_clk inside an always block triggered by clk, but gated_clk is used as a clock signal, which is unsafe.

2. Step 2: Understand timing issues

   Clock gating should be done with combinational logic (AND gate), not inside sequential always block to avoid glitches and timing problems.

3. Final Answer:

   Using gated_clk as a clock signal inside always block causes timing issues -> Option A

4. Quick Check:

   Clock gating must be combinational, not sequential [OK]

Hint: Clock gating must be combinational logic, not inside always block [OK]

Common Mistakes:

• Trying to gate clock inside always @(posedge clk)
• Ignoring timing hazards from gated clocks
• Assuming nonblocking assignment fixes clock gating issues

5. You want to implement clock gating to reduce power in a design where the enable signal is generated asynchronously. Which approach is safest to avoid timing problems?

hard

A. Synchronize the enable signal to the clock domain before gating

B. Use an AND gate with the clock and enable directly without synchronization

C. Invert the enable signal and AND with clock

D. Use an OR gate between clock and enable for gating

Solution

1. Step 1: Understand asynchronous enable risks

   An asynchronous enable can cause glitches or timing violations if used directly for clock gating.

2. Step 2: Choose safe gating method

   Synchronizing the enable signal to the clock domain ensures stable gating and avoids glitches.

3. Final Answer:

   Synchronize the enable signal to the clock domain before gating -> Option A

4. Quick Check:

   Sync async enable before gating clock [OK]

Hint: Always synchronize async enable before clock gating [OK]

Common Mistakes:

• Using async enable directly causing glitches
• Using OR gate instead of AND for gating
• Inverting enable signal incorrectly