Clock gating for power reduction in Verilog - Mini Project: Build & Apply

Clock gating for power reduction

📖 Scenario: In digital circuits, clock signals drive many components. But when parts of the circuit are not active, the clock still toggles and wastes power. Clock gating is a technique to save power by stopping the clock signal to inactive parts.Imagine a simple circuit with a register that only needs to update when an enable signal is high. We want to add clock gating to reduce power use.

🎯 Goal: You will create a Verilog module that uses clock gating to control when a register updates. You will start by defining the register and signals, then add a gated clock signal, and finally show the output value.

📋 What You'll Learn

Create a register to hold an 8-bit value

Add an enable signal to control updating

Create a gated clock signal that only toggles when enable is high

Update the register only on the gated clock's rising edge

Print the register value to verify correct operation

💡 Why This Matters

🌍 Real World

Clock gating is widely used in chips to reduce power consumption by stopping the clock signal to parts of the circuit that are idle.

💼 Career

Understanding clock gating is important for hardware engineers working on low-power digital design and verification.

1

Define the register and input signals

Create a Verilog module named clock_gating with inputs clk, reset, and enable. Inside, declare an 8-bit register called data_reg initialized to 0.

Verilog

module clock_gating(input clk, input reset, input enable);
  reg [7:0] data_reg = 8'b0;
  // Your code here
endmodule

Hint

Start by writing the module header with the three inputs. Then declare data_reg as an 8-bit register initialized to zero.

2

Create the gated clock signal

Inside the clock_gating module, declare a wire called gated_clk that is the logical AND of clk and enable.

Verilog

module clock_gating(input clk, input reset, input enable);
  reg [7:0] data_reg = 8'b0;
  wire gated_clk = clk & enable;
  // Your code here
endmodule

Hint

Use a wire to combine clk and enable with the AND operator.

3

Update the register on gated clock's rising edge

Add an always block triggered on the rising edge of gated_clk or when reset is high. Inside, if reset is high, set data_reg to 0; otherwise, increment data_reg by 1.

Verilog

module clock_gating(input clk, input reset, input enable);
  reg [7:0] data_reg = 8'b0;
  wire gated_clk = clk & enable;

  always @(posedge gated_clk or posedge reset) begin
    // Your code here
  end
endmodule

Hint

Use a synchronous reset and increment data_reg only when gated_clk rises.

4

Display the register value

Add an initial block that uses a $monitor statement to print the current simulation time and the value of data_reg whenever it changes.

Verilog

module clock_gating(input clk, input reset, input enable);
  reg [7:0] data_reg = 8'b0;
  wire gated_clk = clk & enable;

  always @(posedge gated_clk or posedge reset) begin
    if (reset) begin
      data_reg <= 8'b0;
    end else begin
      data_reg <= data_reg + 1;
    end
  end

  initial begin
    // Your code here
  end
endmodule

Hint

Use $monitor inside an initial block to print the time and data_reg value whenever it changes.

Practice

1. What is the main purpose of clock gating in Verilog designs?

easy

A. To increase the clock frequency for faster operation

B. To reduce power consumption by disabling the clock to inactive modules

C. To add delay to the clock signal intentionally

D. To synchronize multiple clock domains

Solution

1. Step 1: Understand clock gating concept

   Clock gating is used to save power by stopping the clock signal to parts of the circuit that are not active.

2. Step 2: Identify the main goal

   The main goal is to reduce power consumption, not to increase speed or add delay.

3. Final Answer:

   To reduce power consumption by disabling the clock to inactive modules -> Option B

4. Quick Check:

   Clock gating = power saving [OK]

Hint: Clock gating stops clock to idle parts to save power [OK]

Common Mistakes:

• Thinking clock gating speeds up the circuit
• Confusing clock gating with clock synchronization
• Assuming clock gating adds intentional delay

2. Which of the following is the correct way to implement clock gating in Verilog?

easy

A. assign gated_clk = ~clk & enable;

B. assign gated_clk = clk | enable;

C. assign gated_clk = clk & enable;

D. assign gated_clk = clk ^ enable;

Solution

1. Step 1: Recall clock gating logic

   Clock gating is done by ANDing the clock with an enable signal to stop the clock when enable is low.

2. Step 2: Check each option

   Only assign gated_clk = clk & enable; uses AND (&) between clock and enable, which is correct for gating.

3. Final Answer:

   assign gated_clk = clk & enable; -> Option C

4. Quick Check:

   Clock gating = clk AND enable [OK]

Hint: Clock gating uses AND between clock and enable [OK]

Common Mistakes:

• Using OR or XOR instead of AND for gating
• Negating clock signal incorrectly
• Confusing enable signal polarity

3. Given the following Verilog snippet, what is the value of gated_clk when clk=1 and enable=0?

assign gated_clk = clk & enable;

medium

A. X (unknown)

B. 1

C. Z (high impedance)

D. 0

Solution

1. Step 1: Evaluate the AND operation

   gated_clk = clk & enable = 1 & 0 = 0.

2. Step 2: Understand output value

   Since enable is 0, gated_clk is forced to 0 regardless of clk.

3. Final Answer:

   0 -> Option D

4. Quick Check:

   1 AND 0 = 0 [OK]

Hint: AND with zero always gives zero [OK]

Common Mistakes:

• Assuming gated_clk equals clk regardless of enable
• Confusing zero with unknown or high impedance
• Thinking gated_clk is always 1 when clk is 1

4. Identify the error in this clock gating code snippet:

module clk_gate(input clk, input enable, output gated_clk);
  always @(posedge clk) begin
    if (enable)
      gated_clk <= clk;
    else
      gated_clk <= 0;
  end
endmodule

medium

A. Using gated_clk as a clock signal inside always block causes timing issues

B. Missing sensitivity to enable signal in always block

C. Incorrect use of nonblocking assignment for gated_clk

D. No error; code is correct

Solution

1. Step 1: Analyze clock gating implementation

   The code tries to assign gated_clk inside an always block triggered by clk, but gated_clk is used as a clock signal, which is unsafe.

2. Step 2: Understand timing issues

   Clock gating should be done with combinational logic (AND gate), not inside sequential always block to avoid glitches and timing problems.

3. Final Answer:

   Using gated_clk as a clock signal inside always block causes timing issues -> Option A

4. Quick Check:

   Clock gating must be combinational, not sequential [OK]

Hint: Clock gating must be combinational logic, not inside always block [OK]

Common Mistakes:

• Trying to gate clock inside always @(posedge clk)
• Ignoring timing hazards from gated clocks
• Assuming nonblocking assignment fixes clock gating issues

5. You want to implement clock gating to reduce power in a design where the enable signal is generated asynchronously. Which approach is safest to avoid timing problems?

hard

A. Synchronize the enable signal to the clock domain before gating

B. Use an AND gate with the clock and enable directly without synchronization

C. Invert the enable signal and AND with clock

D. Use an OR gate between clock and enable for gating

Solution

1. Step 1: Understand asynchronous enable risks

   An asynchronous enable can cause glitches or timing violations if used directly for clock gating.

2. Step 2: Choose safe gating method

   Synchronizing the enable signal to the clock domain ensures stable gating and avoids glitches.

3. Final Answer:

   Synchronize the enable signal to the clock domain before gating -> Option A

4. Quick Check:

   Sync async enable before gating clock [OK]

Hint: Always synchronize async enable before clock gating [OK]

Common Mistakes:

• Using async enable directly causing glitches
• Using OR gate instead of AND for gating
• Inverting enable signal incorrectly