Clock gating for power reduction in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of gated clock signal

What is the output waveform of the gated clock signal `clk_gated` in the following Verilog code snippet when `enable` is high for 4 clock cycles and then low for 4 clock cycles?

Verilog

module clock_gating_example(
  input wire clk,
  input wire enable,
  output wire clk_gated
);

  assign clk_gated = clk & enable;

endmodule

A clk_gated toggles with clk only when enable is high; stays low when enable is low

B clk_gated toggles with clk only when enable is low; stays high when enable is high

C clk_gated is always low regardless of clk and enable

D clk_gated is always the same as clk regardless of enable

💡 Hint

Think about how the AND operation affects the clock signal when enable is 0 or 1.

The gated clock `clk_gated` is the logical AND of `clk` and `enable`. When `enable` is high (1), `clk_gated` follows `clk`. When `enable` is low (0), `clk_gated` stays low, effectively disabling the clock.

🧠 Conceptual

intermediate

Purpose of clock gating in power reduction

Which of the following best describes the main purpose of clock gating in digital circuits?

A To reduce dynamic power consumption by disabling the clock to inactive modules

B To increase the clock frequency for faster operation

C To generate multiple clock domains from a single clock source

D To synchronize asynchronous signals between modules

💡 Hint

Think about what happens when a clock signal is stopped from toggling in parts of a circuit.

Clock gating reduces dynamic power by stopping the clock signal to parts of the circuit that are not currently active, preventing unnecessary switching and saving power.

🔧 Debug

advanced

Identify the error in clock gating implementation

What is the main problem with the following clock gating code snippet?

Verilog

module faulty_clock_gating(
  input wire clk,
  input wire enable,
  output reg clk_gated
);

  always @(posedge clk) begin
    if (enable)
      clk_gated <= ~clk_gated;
    else
      clk_gated <= clk_gated;
  end

endmodule

A clk_gated is toggled asynchronously causing glitches

B clk_gated is generated inside an always block triggered by clk, causing clock domain issues

C enable signal is not synchronized to clk causing metastability

D clk_gated is not a clock signal but a toggled register, which is not a proper gated clock

💡 Hint

Consider what a clock gating signal should be and how it should behave.

The code tries to generate a gated clock by toggling a register on clk edges, but this is not a proper clock gating method. The gated clock should be a combinational AND of clk and enable to avoid glitches and timing issues.

📝 Syntax

advanced

Syntax error in clock gating module

Which option contains the correct syntax to implement a clock gating cell using an enable signal in Verilog?

A assign gated_clk = clk && enable;

B assign gated_clk = clk & enable;

C assign gated_clk = clk | enable;

D assign gated_clk = clk &&& enable;

💡 Hint

Remember the difference between bitwise and logical operators in Verilog.

The bitwise AND operator '&' is used to gate the clock signal with enable. Logical AND '&&' is not valid for bitwise operations on wires.

🚀 Application

expert

Calculate power savings from clock gating

A digital module consumes 100mW dynamic power when clocked continuously. If clock gating disables the clock 60% of the time without affecting functionality, what is the expected dynamic power consumption?

A 100mW

B 60mW

C 40mW

D 160mW

💡 Hint

Dynamic power is proportional to clock activity. Reducing clock activity reduces power proportionally.

If the clock is disabled 60% of the time, the module is active only 40% of the time. So, dynamic power reduces to 40% of 100mW = 40mW.

Practice

1. What is the main purpose of clock gating in Verilog designs?

easy

A. To increase the clock frequency for faster operation

B. To reduce power consumption by disabling the clock to inactive modules

C. To add delay to the clock signal intentionally

D. To synchronize multiple clock domains

Solution

1. Step 1: Understand clock gating concept

   Clock gating is used to save power by stopping the clock signal to parts of the circuit that are not active.

2. Step 2: Identify the main goal

   The main goal is to reduce power consumption, not to increase speed or add delay.

3. Final Answer:

   To reduce power consumption by disabling the clock to inactive modules -> Option B

4. Quick Check:

   Clock gating = power saving [OK]

Hint: Clock gating stops clock to idle parts to save power [OK]

Common Mistakes:

• Thinking clock gating speeds up the circuit
• Confusing clock gating with clock synchronization
• Assuming clock gating adds intentional delay

2. Which of the following is the correct way to implement clock gating in Verilog?

easy

A. assign gated_clk = ~clk & enable;

B. assign gated_clk = clk | enable;

C. assign gated_clk = clk & enable;

D. assign gated_clk = clk ^ enable;

Solution

1. Step 1: Recall clock gating logic

   Clock gating is done by ANDing the clock with an enable signal to stop the clock when enable is low.

2. Step 2: Check each option

   Only assign gated_clk = clk & enable; uses AND (&) between clock and enable, which is correct for gating.

3. Final Answer:

   assign gated_clk = clk & enable; -> Option C

4. Quick Check:

   Clock gating = clk AND enable [OK]

Hint: Clock gating uses AND between clock and enable [OK]

Common Mistakes:

• Using OR or XOR instead of AND for gating
• Negating clock signal incorrectly
• Confusing enable signal polarity

3. Given the following Verilog snippet, what is the value of gated_clk when clk=1 and enable=0?

assign gated_clk = clk & enable;

medium

A. X (unknown)

B. 1

C. Z (high impedance)

D. 0

Solution

1. Step 1: Evaluate the AND operation

   gated_clk = clk & enable = 1 & 0 = 0.

2. Step 2: Understand output value

   Since enable is 0, gated_clk is forced to 0 regardless of clk.

3. Final Answer:

   0 -> Option D

4. Quick Check:

   1 AND 0 = 0 [OK]

Hint: AND with zero always gives zero [OK]

Common Mistakes:

• Assuming gated_clk equals clk regardless of enable
• Confusing zero with unknown or high impedance
• Thinking gated_clk is always 1 when clk is 1

4. Identify the error in this clock gating code snippet:

module clk_gate(input clk, input enable, output gated_clk);
  always @(posedge clk) begin
    if (enable)
      gated_clk <= clk;
    else
      gated_clk <= 0;
  end
endmodule

medium

A. Using gated_clk as a clock signal inside always block causes timing issues

B. Missing sensitivity to enable signal in always block

C. Incorrect use of nonblocking assignment for gated_clk

D. No error; code is correct

Solution

1. Step 1: Analyze clock gating implementation

   The code tries to assign gated_clk inside an always block triggered by clk, but gated_clk is used as a clock signal, which is unsafe.

2. Step 2: Understand timing issues

   Clock gating should be done with combinational logic (AND gate), not inside sequential always block to avoid glitches and timing problems.

3. Final Answer:

   Using gated_clk as a clock signal inside always block causes timing issues -> Option A

4. Quick Check:

   Clock gating must be combinational, not sequential [OK]

Hint: Clock gating must be combinational logic, not inside always block [OK]

Common Mistakes:

• Trying to gate clock inside always @(posedge clk)
• Ignoring timing hazards from gated clocks
• Assuming nonblocking assignment fixes clock gating issues

5. You want to implement clock gating to reduce power in a design where the enable signal is generated asynchronously. Which approach is safest to avoid timing problems?

hard

A. Synchronize the enable signal to the clock domain before gating

B. Use an AND gate with the clock and enable directly without synchronization

C. Invert the enable signal and AND with clock

D. Use an OR gate between clock and enable for gating

Solution

1. Step 1: Understand asynchronous enable risks

   An asynchronous enable can cause glitches or timing violations if used directly for clock gating.

2. Step 2: Choose safe gating method

   Synchronizing the enable signal to the clock domain ensures stable gating and avoids glitches.

3. Final Answer:

   Synchronize the enable signal to the clock domain before gating -> Option A

4. Quick Check:

   Sync async enable before gating clock [OK]

Hint: Always synchronize async enable before clock gating [OK]

Common Mistakes:

• Using async enable directly causing glitches
• Using OR gate instead of AND for gating
• Inverting enable signal incorrectly