Assertion-based verification basics in Verilog - Step-by-Step Execution

Concept Flow - Assertion-based verification basics

Start Simulation

↓

Run Design Code

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Check Assertion Condition

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Continue

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End or Next Cycle

Simulation runs design code and checks assertion conditions each cycle; if assertion fails, an error is reported.

Execution Sample

Verilog

assert property (@(posedge clk) req |-> ##1 ack);

This assertion checks that whenever 'req' is high at a clock edge, 'ack' must be high one cycle later.

Execution Table

Step	clk	req	ack	Assertion Condition (req -> ack next cycle)	Result	Action
1	0	0	0	Not triggered (req=0)	Pass	Continue
2	1	1	0	req=1, ack next cycle unknown yet	Check next cycle	Wait
3	0	1	1	Previous req=1, ack=1	Pass	Continue
4	1	0	1	req=0	Pass	Continue
5	0	1	0	req=1, ack next cycle unknown yet	Check next cycle	Wait
6	1	0	0	Previous req=1, ack=0	Fail	Report Error
7	0	0	0	req=0	Pass	Continue

💡 Simulation ends or continues after assertion failure or success each cycle.

Variable Tracker

Variable	Start	After Step 1	After Step 2	After Step 3	After Step 4	After Step 5	After Step 6	After Step 7
clk	0	0	1	0	1	0	1	0
req	0	0	1	1	0	1	0	0
ack	0	0	0	1	1	0	0	0

Key Moments - 2 Insights

Why does the assertion check 'ack' one cycle after 'req' is high?

Because the assertion uses '##1' which means it looks one clock cycle after 'req' to verify 'ack'. See execution_table steps 2 and 3 where 'req' is 1 and 'ack' is checked next cycle.

What happens when the assertion condition fails?

At step 6, 'req' was 1 previously but 'ack' was 0 next cycle, so the assertion fails and an error is reported, stopping or flagging the simulation.

Visual Quiz - 3 Questions

Look at the execution_table at step 3, what is the value of 'ack'?

A 1

B 0

C Unknown

D Not checked

💡 Hint

Check the 'ack' column in execution_table row for step 3.

At which step does the assertion fail?

A Step 4

B Step 6

C Step 2

D Step 7

💡 Hint

Look at the 'Result' and 'Action' columns in execution_table for failure indication.

If 'ack' was always 1 after 'req' is 1, what would happen in the execution_table?

A Assertion would always pass

B Assertion would fail at step 6

C Simulation would stop early

D No assertion checks would run

💡 Hint

Refer to the 'Result' column in execution_table where 'ack' matches expected value.

Concept Snapshot

Assertion syntax: assert property (@(posedge clk) condition);
Checks if condition holds at clock edges.
Use '##1' to check next cycle.
If condition fails, simulation reports error.
Helps catch design bugs early during simulation.

Full Transcript

In assertion-based verification, simulation runs the design and checks assertions at each clock cycle. Assertions are conditions that must be true, like 'if request is high, acknowledge must be high next cycle'. The simulation checks these conditions step-by-step. If an assertion fails, it reports an error to help find bugs. This example shows how 'req' and 'ack' signals are checked over time, and how the assertion passes or fails depending on their values.

Practice

1. What is the main purpose of an assertion in Verilog verification?

easy

A. To declare variables for testbench

B. To generate synthesis code for hardware

C. To automatically check if a condition is true during simulation

D. To optimize the design for speed

Solution

1. Step 1: Understand what assertions do

   Assertions are used to check if certain conditions hold true automatically during simulation.

2. Step 2: Differentiate from other Verilog constructs

   Assertions do not generate hardware or declare variables; they only verify behavior during simulation.

3. Final Answer:

   To automatically check if a condition is true during simulation -> Option C

4. Quick Check:

   Assertions check conditions automatically [OK]

Hint: Assertions check conditions during simulation automatically [OK]

Common Mistakes:

• Confusing assertions with synthesis code
• Thinking assertions declare variables
• Assuming assertions optimize hardware

2. Which of the following is the correct syntax to write a simple immediate assertion in Verilog?

easy

A. assert property (signal == 1'b1);

B. assert(signal == 1'b1);

C. assert property signal == 1'b1;

D. assert(signal = 1'b1);

Solution

1. Step 1: Recall immediate assertion syntax

   The correct syntax for a simple immediate assertion is 'assert (condition);'.

2. Step 2: Check each option for syntax correctness

   assert(signal == 1'b1); matches the immediate assertion syntax. assert property (signal == 1'b1); uses 'assert property' which is for concurrent assertions. assert property signal == 1'b1; misses parentheses after 'property'. assert(signal = 1'b1); uses assignment '=' instead of comparison '=='.

3. Final Answer:

   assert(signal == 1'b1); -> Option B

4. Quick Check:

   Immediate assertion syntax: 'assert (condition);' [OK]

Hint: Immediate assertions use 'assert (condition);' with '==' for comparison [OK]

Common Mistakes:

• Using 'assert property' for immediate assertions
• Missing parentheses around condition
• Using '=' instead of '==' for comparison

3. Given the assertion: assert property (@(posedge clk) (data != 0)); What happens if data is zero at a clock edge during simulation?

medium

A. The assertion ignores the zero value

B. The assertion passes silently

C. The simulation stops immediately without message

D. The assertion fails and reports an error

Solution

1. Step 1: Understand the assertion condition

   The assertion checks at every positive clock edge that 'data' is not zero.

2. Step 2: Analyze what happens if 'data' equals zero

   If 'data' is zero at a clock edge, the condition 'data != 0' is false, so the assertion fails and reports an error.

3. Final Answer:

   The assertion fails and reports an error -> Option D

4. Quick Check:

   Assertion fails if condition is false at check time [OK]

Hint: Assertion fails if condition is false at check time [OK]

Common Mistakes:

• Thinking assertion passes when condition is false
• Assuming simulation stops silently
• Believing assertion ignores failures

4. Identify the error in this assertion code snippet:

assert property @(posedge clk) (reset == 1'b0);

medium

A. Incorrect use of 'assert property' without parentheses around condition

B. No error, the assertion is correct

C. Using '==' instead of '=' for comparison

D. Missing parentheses around the clock event

Solution

1. Step 1: Check assertion syntax for event and condition

   The correct syntax requires parentheses around the entire property expression, including the event and condition.

2. Step 2: Identify missing parentheses

   The code misses parentheses around '@(posedge clk) (reset == 1'b0)', which is required for 'assert property'.

3. Final Answer:

   Incorrect use of 'assert property' without parentheses around condition -> Option A

4. Quick Check:

   'assert property' needs parentheses around event and condition [OK]

Hint: Always wrap event and condition in parentheses after 'assert property' [OK]

Common Mistakes:

• Omitting parentheses around event and condition
• Confusing '=' with '=='
• Assuming no parentheses needed for event

5. You want to verify that a signal valid remains high for exactly 3 clock cycles after it goes high. Which assertion best captures this behavior?

hard

A. assert property (@(posedge clk) valid |-> valid ##1 valid ##1 !valid);

B. assert property (@(posedge clk) valid |-> ##3 valid);

C. assert property (@(posedge clk) valid |-> ##1 valid ##1 valid ##1 !valid);

D. assert property (@(posedge clk) valid ##3 valid);

Solution

1. Step 1: Understand the requirement

   The signal 'valid' must stay high for exactly 3 clock cycles after it goes high, then go low.

2. Step 2: Analyze each assertion

   assert property (@(posedge clk) valid |-> valid ##1 valid ##1 !valid); uses '|->' implication and timing control to check 'valid' at current cycle, then stays high for 2 more cycles, then low at the 4th cycle, matching exactly 3 cycles high.

3. Step 3: Eliminate incorrect options

   assert property (@(posedge clk) valid |-> ##1 valid ##1 valid ##1 !valid); checks 4 cycles high (3 ##1 delays plus !valid at 4th). assert property (@(posedge clk) valid |-> ##3 valid); checks only after 3 cycles, not duration. assert property (@(posedge clk) valid ##3 valid); lacks implication operator and timing control.

4. Final Answer:

   assert property (@(posedge clk) valid |-> valid ##1 valid ##1 !valid); -> Option A

5. Quick Check:

   Use '|->' with timing to check exact cycle count [OK]

Hint: Use '|->' and timing controls to check exact cycles [OK]

Common Mistakes:

• Confusing number of cycles with delays
• Missing implication operator '|->'
• Incorrect timing control syntax