Assertion-based verification basics in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a simple assertion that checks if signal 'valid' is high.

Verilog

assert property (@(posedge clk) [1]);

Drag options to blanks, or click blank then click option'

Avalid = 1

Bvalid == 1

Cvalid != 1

Dvalid === 0

Attempts:

3 left

💡 Hint

Common Mistakes

Using single '=' instead of '==' for comparison.

Checking for 'valid === 0' which is the opposite condition.

The assertion checks if 'valid' is equal to 1 at the positive edge of the clock.

2fill in blank

medium

Complete the code to assert that 'ready' signal stays high for one clock cycle after 'start' is high.

Verilog

assert property (@(posedge clk) start |-> [1]);

Drag options to blanks, or click blank then click option'

Aready

Bready ##1 ready

Cready ##1 !ready

D!ready

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'ready ##1 ready' which checks two cycles instead of one.

Using negation '!ready' which is incorrect.

The implication '|->' means when 'start' is high, 'ready' should be high in the next cycle.

3fill in blank

hard

Fix the error in the assertion that checks 'data' equals 8'hFF when 'enable' is high.

Verilog

assert property (@(posedge clk) enable |-> (data [1] 8'hFF));

Drag options to blanks, or click blank then click option'

A==

B=>

C!=

D=

Attempts:

3 left

💡 Hint

Common Mistakes

Using '=' which is assignment, not comparison.

Using '!=' which checks inequality, opposite of requirement.

Use '==' for comparison in assertions, '=' is an assignment and causes error.

4fill in blank

hard

Fill both blanks to create an assertion that checks 'flag' remains low for 3 cycles after 'trigger' is high.

Verilog

assert property (@(posedge clk) trigger |-> (flag [1] 0) [*[2]]);

Drag options to blanks, or click blank then click option'

A==

B!=

C3

D5

Attempts:

3 left

💡 Hint

Common Mistakes

Using '!=' which checks for flag not equal to 0.

Using '[*5]' which checks for 5 cycles instead of 3.

The assertion checks 'flag == 0' for 3 cycles after 'trigger'.

5fill in blank

hard

Fill all three blanks to write an assertion that checks if 'start' is high, then 'done' becomes high within 4 cycles and 'error' stays low.

Verilog

assert property (@(posedge clk) start |-> ([1] ##[1:[2]] done && [3] == 0));

Drag options to blanks, or click blank then click option'

Adone

B4

Cerror

Dstart

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'done' in the first blank which is after the delay operator.

Using wrong delay count other than 4.

Checking 'error' equal to 1 instead of 0.

The assertion means when 'start' is high, within 1 to 4 cycles 'done' must be high and 'error' must be low.

Practice

1. What is the main purpose of an assertion in Verilog verification?

easy

A. To declare variables for testbench

B. To generate synthesis code for hardware

C. To automatically check if a condition is true during simulation

D. To optimize the design for speed

Solution

1. Step 1: Understand what assertions do

   Assertions are used to check if certain conditions hold true automatically during simulation.

2. Step 2: Differentiate from other Verilog constructs

   Assertions do not generate hardware or declare variables; they only verify behavior during simulation.

3. Final Answer:

   To automatically check if a condition is true during simulation -> Option C

4. Quick Check:

   Assertions check conditions automatically [OK]

Hint: Assertions check conditions during simulation automatically [OK]

Common Mistakes:

• Confusing assertions with synthesis code
• Thinking assertions declare variables
• Assuming assertions optimize hardware

2. Which of the following is the correct syntax to write a simple immediate assertion in Verilog?

easy

A. assert property (signal == 1'b1);

B. assert(signal == 1'b1);

C. assert property signal == 1'b1;

D. assert(signal = 1'b1);

Solution

1. Step 1: Recall immediate assertion syntax

   The correct syntax for a simple immediate assertion is 'assert (condition);'.

2. Step 2: Check each option for syntax correctness

   assert(signal == 1'b1); matches the immediate assertion syntax. assert property (signal == 1'b1); uses 'assert property' which is for concurrent assertions. assert property signal == 1'b1; misses parentheses after 'property'. assert(signal = 1'b1); uses assignment '=' instead of comparison '=='.

3. Final Answer:

   assert(signal == 1'b1); -> Option B

4. Quick Check:

   Immediate assertion syntax: 'assert (condition);' [OK]

Hint: Immediate assertions use 'assert (condition);' with '==' for comparison [OK]

Common Mistakes:

• Using 'assert property' for immediate assertions
• Missing parentheses around condition
• Using '=' instead of '==' for comparison

3. Given the assertion: assert property (@(posedge clk) (data != 0)); What happens if data is zero at a clock edge during simulation?

medium

A. The assertion ignores the zero value

B. The assertion passes silently

C. The simulation stops immediately without message

D. The assertion fails and reports an error

Solution

1. Step 1: Understand the assertion condition

   The assertion checks at every positive clock edge that 'data' is not zero.

2. Step 2: Analyze what happens if 'data' equals zero

   If 'data' is zero at a clock edge, the condition 'data != 0' is false, so the assertion fails and reports an error.

3. Final Answer:

   The assertion fails and reports an error -> Option D

4. Quick Check:

   Assertion fails if condition is false at check time [OK]

Hint: Assertion fails if condition is false at check time [OK]

Common Mistakes:

• Thinking assertion passes when condition is false
• Assuming simulation stops silently
• Believing assertion ignores failures

4. Identify the error in this assertion code snippet:

assert property @(posedge clk) (reset == 1'b0);

medium

A. Incorrect use of 'assert property' without parentheses around condition

B. No error, the assertion is correct

C. Using '==' instead of '=' for comparison

D. Missing parentheses around the clock event

Solution

1. Step 1: Check assertion syntax for event and condition

   The correct syntax requires parentheses around the entire property expression, including the event and condition.

2. Step 2: Identify missing parentheses

   The code misses parentheses around '@(posedge clk) (reset == 1'b0)', which is required for 'assert property'.

3. Final Answer:

   Incorrect use of 'assert property' without parentheses around condition -> Option A

4. Quick Check:

   'assert property' needs parentheses around event and condition [OK]

Hint: Always wrap event and condition in parentheses after 'assert property' [OK]

Common Mistakes:

• Omitting parentheses around event and condition
• Confusing '=' with '=='
• Assuming no parentheses needed for event

5. You want to verify that a signal valid remains high for exactly 3 clock cycles after it goes high. Which assertion best captures this behavior?

hard

A. assert property (@(posedge clk) valid |-> valid ##1 valid ##1 !valid);

B. assert property (@(posedge clk) valid |-> ##3 valid);

C. assert property (@(posedge clk) valid |-> ##1 valid ##1 valid ##1 !valid);

D. assert property (@(posedge clk) valid ##3 valid);

Solution

1. Step 1: Understand the requirement

   The signal 'valid' must stay high for exactly 3 clock cycles after it goes high, then go low.

2. Step 2: Analyze each assertion

   assert property (@(posedge clk) valid |-> valid ##1 valid ##1 !valid); uses '|->' implication and timing control to check 'valid' at current cycle, then stays high for 2 more cycles, then low at the 4th cycle, matching exactly 3 cycles high.

3. Step 3: Eliminate incorrect options

   assert property (@(posedge clk) valid |-> ##1 valid ##1 valid ##1 !valid); checks 4 cycles high (3 ##1 delays plus !valid at 4th). assert property (@(posedge clk) valid |-> ##3 valid); checks only after 3 cycles, not duration. assert property (@(posedge clk) valid ##3 valid); lacks implication operator and timing control.

4. Final Answer:

   assert property (@(posedge clk) valid |-> valid ##1 valid ##1 !valid); -> Option A

5. Quick Check:

   Use '|->' with timing to check exact cycle count [OK]

Hint: Use '|->' and timing controls to check exact cycles [OK]

Common Mistakes:

• Confusing number of cycles with delays
• Missing implication operator '|->'
• Incorrect timing control syntax