Assertion-based verification basics in Verilog - Mini Project: Build & Apply

Assertion-based verification basics

📖 Scenario: You are designing a simple digital system that has a clock and a reset signal. You want to make sure the reset signal is always active for at least two clock cycles when asserted. This helps catch bugs early in your design.

🎯 Goal: Build a Verilog module with a clock and reset input, then add an assertion to check that the reset signal stays high for at least two clock cycles whenever it goes high.

📋 What You'll Learn

Create a Verilog module named reset_checker with inputs clk and reset

Add a property named reset_duration that checks reset is high for at least two clock cycles

Use an assertion to verify the reset_duration property

Print a message when the assertion fails

💡 Why This Matters

🌍 Real World

Assertions help catch design bugs early by automatically checking signal behavior during simulation.

💼 Career

Verification engineers use assertions to improve design quality and reduce debugging time in hardware projects.

1

Create the Verilog module with clock and reset inputs

Write a Verilog module named reset_checker with inputs clk and reset. Do not add any logic yet.

Verilog

module reset_checker(input clk, input reset);

// Your code here

endmodule

Hint

Start by declaring the module and its inputs exactly as specified.

2

Define the property to check reset duration

Inside the reset_checker module, define a property named reset_duration that checks if reset stays high for at least two consecutive clk cycles.

Verilog

module reset_checker(input clk, input reset);

// Define property reset_duration here

endmodule

Hint

Use the sequence reset |-> ##1 reset to check reset is high now and one clock cycle later.

3

Add an assertion to verify the reset duration property

Add an assertion inside the reset_checker module that checks the reset_duration property on every positive edge of clk.

Verilog

module reset_checker(input clk, input reset);

  property reset_duration;
    @(posedge clk) reset |-> ##1 reset;
  endproperty

  // Add assertion here

endmodule

Hint

Use assert property (reset_duration) and add an else clause with $error to print a message on failure.

4

Simulate and observe assertion output

Write a simple testbench that toggles clk and drives reset high for only one clock cycle. Run the simulation and print the assertion failure message.

Verilog

module testbench;
  reg clk = 0;
  reg reset = 0;

  // Instantiate reset_checker

  // Clock generation

  // Drive reset high for 1 cycle

  // Your code here

endmodule

Hint

Run the simulation and watch for the error message printed by the assertion.

Practice

1. What is the main purpose of an assertion in Verilog verification?

easy

A. To declare variables for testbench

B. To generate synthesis code for hardware

C. To automatically check if a condition is true during simulation

D. To optimize the design for speed

Solution

1. Step 1: Understand what assertions do

   Assertions are used to check if certain conditions hold true automatically during simulation.

2. Step 2: Differentiate from other Verilog constructs

   Assertions do not generate hardware or declare variables; they only verify behavior during simulation.

3. Final Answer:

   To automatically check if a condition is true during simulation -> Option C

4. Quick Check:

   Assertions check conditions automatically [OK]

Hint: Assertions check conditions during simulation automatically [OK]

Common Mistakes:

• Confusing assertions with synthesis code
• Thinking assertions declare variables
• Assuming assertions optimize hardware

2. Which of the following is the correct syntax to write a simple immediate assertion in Verilog?

easy

A. assert property (signal == 1'b1);

B. assert(signal == 1'b1);

C. assert property signal == 1'b1;

D. assert(signal = 1'b1);

Solution

1. Step 1: Recall immediate assertion syntax

   The correct syntax for a simple immediate assertion is 'assert (condition);'.

2. Step 2: Check each option for syntax correctness

   assert(signal == 1'b1); matches the immediate assertion syntax. assert property (signal == 1'b1); uses 'assert property' which is for concurrent assertions. assert property signal == 1'b1; misses parentheses after 'property'. assert(signal = 1'b1); uses assignment '=' instead of comparison '=='.

3. Final Answer:

   assert(signal == 1'b1); -> Option B

4. Quick Check:

   Immediate assertion syntax: 'assert (condition);' [OK]

Hint: Immediate assertions use 'assert (condition);' with '==' for comparison [OK]

Common Mistakes:

• Using 'assert property' for immediate assertions
• Missing parentheses around condition
• Using '=' instead of '==' for comparison

3. Given the assertion: assert property (@(posedge clk) (data != 0)); What happens if data is zero at a clock edge during simulation?

medium

A. The assertion ignores the zero value

B. The assertion passes silently

C. The simulation stops immediately without message

D. The assertion fails and reports an error

Solution

1. Step 1: Understand the assertion condition

   The assertion checks at every positive clock edge that 'data' is not zero.

2. Step 2: Analyze what happens if 'data' equals zero

   If 'data' is zero at a clock edge, the condition 'data != 0' is false, so the assertion fails and reports an error.

3. Final Answer:

   The assertion fails and reports an error -> Option D

4. Quick Check:

   Assertion fails if condition is false at check time [OK]

Hint: Assertion fails if condition is false at check time [OK]

Common Mistakes:

• Thinking assertion passes when condition is false
• Assuming simulation stops silently
• Believing assertion ignores failures

4. Identify the error in this assertion code snippet:

assert property @(posedge clk) (reset == 1'b0);

medium

A. Incorrect use of 'assert property' without parentheses around condition

B. No error, the assertion is correct

C. Using '==' instead of '=' for comparison

D. Missing parentheses around the clock event

Solution

1. Step 1: Check assertion syntax for event and condition

   The correct syntax requires parentheses around the entire property expression, including the event and condition.

2. Step 2: Identify missing parentheses

   The code misses parentheses around '@(posedge clk) (reset == 1'b0)', which is required for 'assert property'.

3. Final Answer:

   Incorrect use of 'assert property' without parentheses around condition -> Option A

4. Quick Check:

   'assert property' needs parentheses around event and condition [OK]

Hint: Always wrap event and condition in parentheses after 'assert property' [OK]

Common Mistakes:

• Omitting parentheses around event and condition
• Confusing '=' with '=='
• Assuming no parentheses needed for event

5. You want to verify that a signal valid remains high for exactly 3 clock cycles after it goes high. Which assertion best captures this behavior?

hard

A. assert property (@(posedge clk) valid |-> valid ##1 valid ##1 !valid);

B. assert property (@(posedge clk) valid |-> ##3 valid);

C. assert property (@(posedge clk) valid |-> ##1 valid ##1 valid ##1 !valid);

D. assert property (@(posedge clk) valid ##3 valid);

Solution

1. Step 1: Understand the requirement

   The signal 'valid' must stay high for exactly 3 clock cycles after it goes high, then go low.

2. Step 2: Analyze each assertion

   assert property (@(posedge clk) valid |-> valid ##1 valid ##1 !valid); uses '|->' implication and timing control to check 'valid' at current cycle, then stays high for 2 more cycles, then low at the 4th cycle, matching exactly 3 cycles high.

3. Step 3: Eliminate incorrect options

   assert property (@(posedge clk) valid |-> ##1 valid ##1 valid ##1 !valid); checks 4 cycles high (3 ##1 delays plus !valid at 4th). assert property (@(posedge clk) valid |-> ##3 valid); checks only after 3 cycles, not duration. assert property (@(posedge clk) valid ##3 valid); lacks implication operator and timing control.

4. Final Answer:

   assert property (@(posedge clk) valid |-> valid ##1 valid ##1 !valid); -> Option A

5. Quick Check:

   Use '|->' with timing to check exact cycle count [OK]

Hint: Use '|->' and timing controls to check exact cycles [OK]

Common Mistakes:

• Confusing number of cycles with delays
• Missing implication operator '|->'
• Incorrect timing control syntax