Using $display and $monitor in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to print the value of signal 'a' once using $display.

Verilog

initial begin
  a = 1'b0;
  #5 a = 1'b1;
  $[1]("Value of a = %b", a);
end

Drag options to blanks, or click blank then click option'

A$display

B$monitor

C$write

D$stop

Attempts:

3 left

💡 Hint

Common Mistakes

Using $monitor instead of $display causes continuous printing.

Using $write does not add a newline automatically.

The $display command prints the message once at the time it is executed.

2fill in blank

medium

Complete the code to continuously print changes of 'b' using $monitor.

Verilog

initial begin
  b = 0;
  $[1]("Time=%0t, b=%b", $time, b);
  #10 b = 1;
  #10 b = 0;
end

Drag options to blanks, or click blank then click option'

A$display

B$monitor

C$write

D$stop

Attempts:

3 left

💡 Hint

Common Mistakes

Using $display causes only one print at start.

Forgetting to include $time in the message for timing info.

The $monitor command prints the message whenever any variable in the message changes.

3fill in blank

hard

Fix the error in the code to correctly display the value of 'c' at time 0.

Verilog

initial begin
  c = 1'b1;
  $[1]("At time %0t, c = %b", $time, c);
end

Drag options to blanks, or click blank then click option'

A$monitor

B$stop

C$write

D$display

Attempts:

3 left

💡 Hint

Common Mistakes

Using $monitor causes repeated prints.

Using $write without newline causes output formatting issues.

Use $display to print the value once at time 0. $monitor would print continuously.

4fill in blank

hard

Fill both blanks to print initial values once and then monitor signals 'x' and 'y'.

Verilog

initial begin
  $[1]("x = %b, y = %b", x, y);
  $[2]("Monitoring signals x and y");
end

Drag options to blanks, or click blank then click option'

A$monitor

B$display

C$write

D$stop

Attempts:

3 left

💡 Hint

Common Mistakes

Reversing the order of $display and $monitor.

Using $write instead of $display for messages.

Use $display for one-time message and $monitor to watch signals continuously.

5fill in blank

hard

Fill all three blanks to display and monitor signals 'p' and 'q' with time info.

Verilog

initial begin
  $[1]("Start time: %0t", $time);
  $[2]("p = %b, q = %b", p, q);
  $[3]("Monitoring p and q changes");
end

Drag options to blanks, or click blank then click option'

A$display

B$monitor

C$write

D$stop

Attempts:

3 left

💡 Hint

Common Mistakes

Using $monitor for start time print causes repeated output.

Using $write without newline causes formatting issues.

Use $display to print start time and messages once, and $monitor to watch signal changes.

Practice

1. What is the main difference between $display and $monitor in Verilog?

easy

A. $display prints continuously; $monitor prints only once.

B. $display prints once when called; $monitor prints whenever a variable changes.

C. $display is used for debugging; $monitor is used for synthesis.

D. $display prints to a file; $monitor prints to the console.

Solution

1. Step 1: Understand $display behavior

   $display prints a message only once at the time it is called during simulation.

2. Step 2: Understand $monitor behavior

   $monitor automatically prints a message every time any of the monitored variables change value.

3. Final Answer:

   $display prints once when called; $monitor prints whenever a variable changes. -> Option B

4. Quick Check:

   $display = once, $monitor = on change [OK]

Hint: Remember: display = one-time print, monitor = auto on change [OK]

Common Mistakes:

• Thinking $display prints continuously
• Confusing $monitor with file output
• Assuming $monitor prints only once

2. Which of the following is the correct syntax to print the value of a 4-bit register reg [3:0] count; using $display?

easy

A. $display("Count value: %d", count);

B. $display("Count value: %h", count);

C. $display("Count value: %s", count);

D. $display("Count value: %b", count);

Solution

1. Step 1: Identify the data type and format specifier

   The register count is 4-bit binary, so binary format specifier %b is appropriate.

2. Step 2: Match format specifier with $display syntax

   $display("Count value: %b", count); correctly prints the binary value of count.

3. Final Answer:

   $display("Count value: %b", count); -> Option D

4. Quick Check:

   Binary format = %b [OK]

Hint: Use %b for binary, %d decimal, %h hex in $display [OK]

Common Mistakes:

• Using %s which is for strings, not numbers
• Using %d for binary values
• Forgetting to include variable after format string

3. Given the following Verilog code snippet, what will be the output during simulation?

reg [1:0] a;
initial begin
  a = 2'b00;
  $monitor("Time=%0t a=%b", $time, a);
  #5 a = 2'b01;
  #5 a = 2'b11;
  #5 a = 2'b10;
end

medium

A. Prints four lines showing time and value of 'a' at 0, 5, 10, and 15 time units.

B. Prints only one line at time 0 with initial value of 'a'.

C. Prints three lines at times 5, 10, and 15 but not at time 0.

D. No output because $monitor is not called correctly.

Solution

1. Step 1: Understand $monitor initial print

   $monitor prints immediately when called (time 0) and then whenever monitored variables change.

2. Step 2: Trace changes to 'a' and timing

   'a' changes at 5, 10, and 15 time units, so $monitor prints at these times plus initial time 0.

3. Final Answer:

   Prints four lines showing time and value of 'a' at 0, 5, 10, and 15 time units. -> Option A

4. Quick Check:

   $monitor prints on call + changes = 4 prints [OK]

Hint: $monitor prints immediately and on every change [OK]

Common Mistakes:

• Assuming $monitor prints only on changes, missing initial print
• Thinking $monitor prints only once
• Confusing $display behavior with $monitor

4. Identify the error in this Verilog code snippet:

reg clk;
initial begin
  $monitor("Clock = %b", clk);
  clk = 0;
  #10 clk = 1;
  #10 clk = 0;
end

medium

A. clk should be declared as wire, not reg, for $monitor to work.

B. Missing semicolon after $monitor statement causes syntax error.

C. $monitor is called before clk is initialized, so initial print shows unknown value.

D. No error; code runs and prints correctly.

Solution

1. Step 1: Check order of $monitor and variable initialization

   $monitor is called before clk is assigned a value, so initial print shows 'x' (unknown).

2. Step 2: Understand $monitor initial print behavior

   $monitor prints immediately on call, so it prints clk's value before initialization.

3. Final Answer:

   $monitor is called before clk is initialized, so initial print shows unknown value. -> Option C

4. Quick Check:

   Initialize variables before $monitor call [OK]

Hint: Initialize variables before $monitor to avoid unknown prints [OK]

Common Mistakes:

• Assuming $monitor waits for variable initialization
• Thinking missing semicolon causes error here
• Confusing reg and wire for $monitor usage

5. You want to monitor two signals reg [3:0] data; and reg valid; so that the simulation prints their values only when valid changes. Which is the best way to do this using $monitor?

hard

A. $monitor("Data=%b Valid=%b", data, valid);

B. Use an if statement inside $monitor to print only when valid changes.

C. Use $monitor with only valid variable: $monitor("Valid=%b", valid); and add $display for data.

D. Use $monitor with both variables but assign data only when valid changes.

Solution

1. Step 1: Understand $monitor behavior with multiple variables

   $monitor prints whenever any monitored variable changes. Monitoring both data and valid prints on either change.

2. Step 2: Restrict printing to valid changes only

   To print only when valid changes, monitor only valid. But then data won't print updated values automatically.

3. Step 3: Best practical approach

   Monitoring both variables prints all changes, but since data changes only when valid changes, this works well. $monitor("Data=%b Valid=%b", data, valid); is simplest and correct.

4. Final Answer:

   $monitor("Data=%b Valid=%b", data, valid); -> Option A

5. Quick Check:

   Monitor all needed vars; prints on any change [OK]

Hint: Monitor all variables to track changes together [OK]

Common Mistakes:

• Trying to put conditions inside $monitor (not allowed)
• Monitoring only one variable and missing others' changes
• Using $display inside $monitor incorrectly