Using $display and $monitor in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this Verilog code using $display?

Consider the following Verilog code snippet. What will be printed on the console when it runs?

Verilog

module test;
  reg a = 0;
  initial begin
    $display("Value of a is %d", a);
    a = 1;
    $display("Value of a changed to %d", a);
  end
endmodule

A

Value of a is 0
Value of a is 0

B

Value of a is 1
Value of a changed to 1

C

Value of a is 0
Value of a changed to 1

D

Value of a changed to 0
Value of a changed to 1

💡 Hint

Remember that $display prints the value at the time it is called.

The first $display prints the initial value of a which is 0. Then a is set to 1, and the second $display prints the updated value.

❓ Predict Output

intermediate

What does this Verilog code print using $monitor?

Look at this Verilog code using $monitor. What output will it produce?

Verilog

module test;
  reg a = 0;
  initial begin
    $monitor("At time %0t, a = %d", $time, a);
    #5 a = 1;
    #5 a = 0;
    #5 $finish;
  end
endmodule

A

At time 0, a = 0
At time 5, a = 1
At time 10, a = 0

B

At time 5, a = 1
At time 10, a = 0

C

At time 0, a = 0
At time 5, a = 0
At time 10, a = 1

D No output because $monitor is not called correctly

💡 Hint

$monitor prints whenever a monitored variable changes, including at time 0.

$monitor prints the initial values at time 0, then prints again whenever a changes at times 5 and 10.

🔧 Debug

advanced

Why does this Verilog code not print any output?

Examine this Verilog code. It uses $monitor but prints nothing. What is the reason?

Verilog

module test;
  reg a = 0;
  initial begin
    $monitor("a = %d", a);
  end
endmodule

A Because <code>a</code> never changes, $monitor does not print after initial call

B Because $monitor requires a semicolon after the format string

C Because $monitor can only be used inside always blocks

D Because the simulation ends immediately without delay, $monitor has no chance to print

💡 Hint

Think about simulation time and when $monitor prints.

$monitor prints immediately at time 0, but if the simulation ends instantly (no delays or events), the output may not appear. Here, the simulation ends immediately after initial block.

📝 Syntax

advanced

Which option causes a syntax error in $display usage?

Which of the following $display statements is syntactically incorrect in Verilog?

A $display("Value is %d" val);

B $display("Value is %d", val);

C $display("Value is %d", val,);

D $display("Value is %d", val + 1);

💡 Hint

Check the commas between arguments carefully.

Option A misses a comma between the format string and the variable, causing a syntax error.

🚀 Application

expert

How many times will $monitor print in this Verilog code?

Given this Verilog code, how many lines will $monitor print before simulation ends?

Verilog

module test;
  reg a = 0;
  reg b = 1;
  initial begin
    $monitor("Time %0t: a=%d, b=%d", $time, a, b);
    #3 a = 1;
    #2 b = 0;
    #5 a = 0;
    #1 $finish;
  end
endmodule

A 3

B 4

C 5

D 2

💡 Hint

$monitor prints at time 0 and whenever any monitored variable changes.

$monitor prints initially at time 0, then at time 3 when a changes, at time 5 when b changes, and at time 10 when a changes again. Total 4 prints.

Practice

1. What is the main difference between $display and $monitor in Verilog?

easy

A. $display prints continuously; $monitor prints only once.

B. $display prints once when called; $monitor prints whenever a variable changes.

C. $display is used for debugging; $monitor is used for synthesis.

D. $display prints to a file; $monitor prints to the console.

Solution

1. Step 1: Understand $display behavior

   $display prints a message only once at the time it is called during simulation.

2. Step 2: Understand $monitor behavior

   $monitor automatically prints a message every time any of the monitored variables change value.

3. Final Answer:

   $display prints once when called; $monitor prints whenever a variable changes. -> Option B

4. Quick Check:

   $display = once, $monitor = on change [OK]

Hint: Remember: display = one-time print, monitor = auto on change [OK]

Common Mistakes:

• Thinking $display prints continuously
• Confusing $monitor with file output
• Assuming $monitor prints only once

2. Which of the following is the correct syntax to print the value of a 4-bit register reg [3:0] count; using $display?

easy

A. $display("Count value: %d", count);

B. $display("Count value: %h", count);

C. $display("Count value: %s", count);

D. $display("Count value: %b", count);

Solution

1. Step 1: Identify the data type and format specifier

   The register count is 4-bit binary, so binary format specifier %b is appropriate.

2. Step 2: Match format specifier with $display syntax

   $display("Count value: %b", count); correctly prints the binary value of count.

3. Final Answer:

   $display("Count value: %b", count); -> Option D

4. Quick Check:

   Binary format = %b [OK]

Hint: Use %b for binary, %d decimal, %h hex in $display [OK]

Common Mistakes:

• Using %s which is for strings, not numbers
• Using %d for binary values
• Forgetting to include variable after format string

3. Given the following Verilog code snippet, what will be the output during simulation?

reg [1:0] a;
initial begin
  a = 2'b00;
  $monitor("Time=%0t a=%b", $time, a);
  #5 a = 2'b01;
  #5 a = 2'b11;
  #5 a = 2'b10;
end

medium

A. Prints four lines showing time and value of 'a' at 0, 5, 10, and 15 time units.

B. Prints only one line at time 0 with initial value of 'a'.

C. Prints three lines at times 5, 10, and 15 but not at time 0.

D. No output because $monitor is not called correctly.

Solution

1. Step 1: Understand $monitor initial print

   $monitor prints immediately when called (time 0) and then whenever monitored variables change.

2. Step 2: Trace changes to 'a' and timing

   'a' changes at 5, 10, and 15 time units, so $monitor prints at these times plus initial time 0.

3. Final Answer:

   Prints four lines showing time and value of 'a' at 0, 5, 10, and 15 time units. -> Option A

4. Quick Check:

   $monitor prints on call + changes = 4 prints [OK]

Hint: $monitor prints immediately and on every change [OK]

Common Mistakes:

• Assuming $monitor prints only on changes, missing initial print
• Thinking $monitor prints only once
• Confusing $display behavior with $monitor

4. Identify the error in this Verilog code snippet:

reg clk;
initial begin
  $monitor("Clock = %b", clk);
  clk = 0;
  #10 clk = 1;
  #10 clk = 0;
end

medium

A. clk should be declared as wire, not reg, for $monitor to work.

B. Missing semicolon after $monitor statement causes syntax error.

C. $monitor is called before clk is initialized, so initial print shows unknown value.

D. No error; code runs and prints correctly.

Solution

1. Step 1: Check order of $monitor and variable initialization

   $monitor is called before clk is assigned a value, so initial print shows 'x' (unknown).

2. Step 2: Understand $monitor initial print behavior

   $monitor prints immediately on call, so it prints clk's value before initialization.

3. Final Answer:

   $monitor is called before clk is initialized, so initial print shows unknown value. -> Option C

4. Quick Check:

   Initialize variables before $monitor call [OK]

Hint: Initialize variables before $monitor to avoid unknown prints [OK]

Common Mistakes:

• Assuming $monitor waits for variable initialization
• Thinking missing semicolon causes error here
• Confusing reg and wire for $monitor usage

5. You want to monitor two signals reg [3:0] data; and reg valid; so that the simulation prints their values only when valid changes. Which is the best way to do this using $monitor?

hard

A. $monitor("Data=%b Valid=%b", data, valid);

B. Use an if statement inside $monitor to print only when valid changes.

C. Use $monitor with only valid variable: $monitor("Valid=%b", valid); and add $display for data.

D. Use $monitor with both variables but assign data only when valid changes.

Solution

1. Step 1: Understand $monitor behavior with multiple variables

   $monitor prints whenever any monitored variable changes. Monitoring both data and valid prints on either change.

2. Step 2: Restrict printing to valid changes only

   To print only when valid changes, monitor only valid. But then data won't print updated values automatically.

3. Step 3: Best practical approach

   Monitoring both variables prints all changes, but since data changes only when valid changes, this works well. $monitor("Data=%b Valid=%b", data, valid); is simplest and correct.

4. Final Answer:

   $monitor("Data=%b Valid=%b", data, valid); -> Option A

5. Quick Check:

   Monitor all needed vars; prints on any change [OK]

Hint: Monitor all variables to track changes together [OK]

Common Mistakes:

• Trying to put conditions inside $monitor (not allowed)
• Monitoring only one variable and missing others' changes
• Using $display inside $monitor incorrectly