Using $display and $monitor in Verilog - Time & Space Complexity

Time Complexity: Using $display and $monitor

O(n)

Understanding Time Complexity

We want to understand how the time cost changes when using $display and $monitor in Verilog simulations.

How does the number of print operations grow as the simulation runs longer or with more changes?

Scenario Under Consideration

Analyze the time complexity of the following code snippet.

module test;
  reg clk;
  reg [3:0] count;

  initial begin
    clk = 0;
    count = 0;
    forever #5 clk = ~clk;
  end

  always @(posedge clk) begin
    count = count + 1;
    $display("Count is %d", count);
  end

  initial $monitor("At time %0t, count = %d", $time, count);
endmodule
    

This code toggles a clock and increments a counter on each positive clock edge. It uses $display to print the count each time it changes and $monitor to print whenever count changes.

Identify Repeating Operations

Identify the loops, recursion, array traversals that repeat.

• Primary operation: The $display statement runs once every positive clock edge.
• Secondary operation: The $monitor prints whenever the count changes, which happens every clock edge as well.
• How many times: Both print operations happen once per clock cycle, repeating indefinitely.

How Execution Grows With Input

As the number of clock cycles (n) increases, the number of print operations grows linearly.

Input Size (n = clock cycles)	Approx. Print Operations
10	About 20 prints
100	About 200 prints
1000	About 2000 prints

Pattern observation: The number of print statements grows directly with the number of clock cycles.

Final Time Complexity

Time Complexity: O(n)

This means the time spent printing grows in a straight line as the simulation runs longer.

Common Mistake

[X] Wrong: "$monitor only prints once, so it does not affect time complexity much."

[OK] Correct: $monitor prints every time the watched variable changes, which can be many times, so it adds up linearly with input size.

Interview Connect

Understanding how print statements affect simulation time helps you write efficient testbenches and debug code without slowing down your simulation too much.

Self-Check

"What if we replaced $display with $write inside the always block? How would the time complexity change?"

Practice

1. What is the main difference between $display and $monitor in Verilog?

easy

A. $display prints continuously; $monitor prints only once.

B. $display prints once when called; $monitor prints whenever a variable changes.

C. $display is used for debugging; $monitor is used for synthesis.

D. $display prints to a file; $monitor prints to the console.

Solution

1. Step 1: Understand $display behavior

   $display prints a message only once at the time it is called during simulation.

2. Step 2: Understand $monitor behavior

   $monitor automatically prints a message every time any of the monitored variables change value.

3. Final Answer:

   $display prints once when called; $monitor prints whenever a variable changes. -> Option B

4. Quick Check:

   $display = once, $monitor = on change [OK]

Hint: Remember: display = one-time print, monitor = auto on change [OK]

Common Mistakes:

• Thinking $display prints continuously
• Confusing $monitor with file output
• Assuming $monitor prints only once

2. Which of the following is the correct syntax to print the value of a 4-bit register reg [3:0] count; using $display?

easy

A. $display("Count value: %d", count);

B. $display("Count value: %h", count);

C. $display("Count value: %s", count);

D. $display("Count value: %b", count);

Solution

1. Step 1: Identify the data type and format specifier

   The register count is 4-bit binary, so binary format specifier %b is appropriate.

2. Step 2: Match format specifier with $display syntax

   $display("Count value: %b", count); correctly prints the binary value of count.

3. Final Answer:

   $display("Count value: %b", count); -> Option D

4. Quick Check:

   Binary format = %b [OK]

Hint: Use %b for binary, %d decimal, %h hex in $display [OK]

Common Mistakes:

• Using %s which is for strings, not numbers
• Using %d for binary values
• Forgetting to include variable after format string

3. Given the following Verilog code snippet, what will be the output during simulation?

reg [1:0] a;
initial begin
  a = 2'b00;
  $monitor("Time=%0t a=%b", $time, a);
  #5 a = 2'b01;
  #5 a = 2'b11;
  #5 a = 2'b10;
end

medium

A. Prints four lines showing time and value of 'a' at 0, 5, 10, and 15 time units.

B. Prints only one line at time 0 with initial value of 'a'.

C. Prints three lines at times 5, 10, and 15 but not at time 0.

D. No output because $monitor is not called correctly.

Solution

1. Step 1: Understand $monitor initial print

   $monitor prints immediately when called (time 0) and then whenever monitored variables change.

2. Step 2: Trace changes to 'a' and timing

   'a' changes at 5, 10, and 15 time units, so $monitor prints at these times plus initial time 0.

3. Final Answer:

   Prints four lines showing time and value of 'a' at 0, 5, 10, and 15 time units. -> Option A

4. Quick Check:

   $monitor prints on call + changes = 4 prints [OK]

Hint: $monitor prints immediately and on every change [OK]

Common Mistakes:

• Assuming $monitor prints only on changes, missing initial print
• Thinking $monitor prints only once
• Confusing $display behavior with $monitor

4. Identify the error in this Verilog code snippet:

reg clk;
initial begin
  $monitor("Clock = %b", clk);
  clk = 0;
  #10 clk = 1;
  #10 clk = 0;
end

medium

A. clk should be declared as wire, not reg, for $monitor to work.

B. Missing semicolon after $monitor statement causes syntax error.

C. $monitor is called before clk is initialized, so initial print shows unknown value.

D. No error; code runs and prints correctly.

Solution

1. Step 1: Check order of $monitor and variable initialization

   $monitor is called before clk is assigned a value, so initial print shows 'x' (unknown).

2. Step 2: Understand $monitor initial print behavior

   $monitor prints immediately on call, so it prints clk's value before initialization.

3. Final Answer:

   $monitor is called before clk is initialized, so initial print shows unknown value. -> Option C

4. Quick Check:

   Initialize variables before $monitor call [OK]

Hint: Initialize variables before $monitor to avoid unknown prints [OK]

Common Mistakes:

• Assuming $monitor waits for variable initialization
• Thinking missing semicolon causes error here
• Confusing reg and wire for $monitor usage

5. You want to monitor two signals reg [3:0] data; and reg valid; so that the simulation prints their values only when valid changes. Which is the best way to do this using $monitor?

hard

A. $monitor("Data=%b Valid=%b", data, valid);

B. Use an if statement inside $monitor to print only when valid changes.

C. Use $monitor with only valid variable: $monitor("Valid=%b", valid); and add $display for data.

D. Use $monitor with both variables but assign data only when valid changes.

Solution

1. Step 1: Understand $monitor behavior with multiple variables

   $monitor prints whenever any monitored variable changes. Monitoring both data and valid prints on either change.

2. Step 2: Restrict printing to valid changes only

   To print only when valid changes, monitor only valid. But then data won't print updated values automatically.

3. Step 3: Best practical approach

   Monitoring both variables prints all changes, but since data changes only when valid changes, this works well. $monitor("Data=%b Valid=%b", data, valid); is simplest and correct.

4. Final Answer:

   $monitor("Data=%b Valid=%b", data, valid); -> Option A

5. Quick Check:

   Monitor all needed vars; prints on any change [OK]

Hint: Monitor all variables to track changes together [OK]

Common Mistakes:

• Trying to put conditions inside $monitor (not allowed)
• Monitoring only one variable and missing others' changes
• Using $display inside $monitor incorrectly