Simulation vs synthesis mental model in Verilog - Interactive Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a 4-bit register in Verilog.

Verilog

reg [[1]:0] my_reg;

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A3

B4

C7

D0

Attempts:

3 left

💡 Hint

Common Mistakes

Using 4 instead of 3 as the highest index.

In Verilog, a 4-bit register is declared as reg [3:0] because the index starts at 0.

2fill in blank

medium

Complete the code to assign a value to a register inside an always block for simulation.

Verilog

always @(posedge clk) begin
  [1] <= data_in;
end

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Areg my_reg

Bwire my_reg

Cassign my_reg

Dmy_reg

Attempts:

3 left

💡 Hint

Common Mistakes

Using 'assign' keyword inside always block.

Inside an always block, you assign values to registers directly by their name, here my_reg.

3fill in blank

hard

Fix the error in the code to make it synthesizable: a combinational always block.

Verilog

always @([1]) begin
  out = a & b;
end

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Aposedge clk

Ba or b

Cnegedge reset

Dclk or reset

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock edges in combinational always block sensitivity list.

For combinational logic, the sensitivity list must include all inputs, here a or b.

4fill in blank

hard

Fill both blanks to complete a synthesizable flip-flop with asynchronous reset.

Verilog

always @([1] or [2]) begin
  if (!reset) out <= 0;
  else out <= d;
end

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Aposedge clk

Bnegedge reset

Cposedge reset

Dnegedge clk

Attempts:

3 left

💡 Hint

Common Mistakes

Using posedge reset for asynchronous reset.

The flip-flop triggers on the rising edge of the clock and the falling edge of the asynchronous reset.

5fill in blank

hard

Fill all three blanks to create a dictionary-like mapping using a case statement for synthesis.

Verilog

always @(*) begin
  case (addr)
    2'b00: data = [1];
    2'b01: data = [2];
    default: data = [3];
  endcase
end

Drag options to blanks, or click blank then click option'

A8'hFF

B8'h00

C8'hAA

D8'h55

Attempts:

3 left

💡 Hint

Common Mistakes

Using invalid values or missing default case.

The case statement assigns different 8-bit hex values based on the address input.

Practice

1. What is the main purpose of simulation in Verilog?

easy

A. To convert the design into physical hardware

B. To check how the design behaves over time step-by-step

C. To write the final hardware layout

D. To optimize the hardware speed automatically

Solution

1. Step 1: Understand simulation role

   Simulation runs the design in a virtual environment to see how it behaves over time.

2. Step 2: Compare with synthesis role

   Synthesis is about creating hardware, not checking behavior step-by-step.

3. Final Answer:

   To check how the design behaves over time step-by-step -> Option B

4. Quick Check:

   Simulation = behavior check [OK]

Hint: Simulation means testing behavior over time, not hardware creation [OK]

Common Mistakes:

• Confusing synthesis with simulation
• Thinking simulation creates hardware
• Believing simulation optimizes hardware

2. Which of the following is a correct Verilog syntax for a simple always block used in simulation?

easy

A. always @(posedge clk) begin count = count + 1; end

B. always posedge clk { count = count + 1; }

C. always @(clk) count <= count + 1;

D. always #10 count = count + 1

Solution

1. Step 1: Check correct always block syntax

   The correct syntax uses 'always @(posedge clk) begin ... end' with proper parentheses and keywords.

2. Step 2: Identify syntax errors in other options

   always posedge clk { count = count + 1; } uses braces and wrong syntax; C uses wrong sensitivity list; D uses delay but lacks begin-end block.

3. Final Answer:

   always @(posedge clk) begin count = count + 1; end -> Option A

4. Quick Check:

   Correct always block syntax = always @(posedge clk) begin count = count + 1; end [OK]

Hint: Always blocks use @(event) with begin-end for multiple statements [OK]

Common Mistakes:

• Using braces {} instead of begin-end
• Wrong sensitivity list syntax
• Missing begin-end for multiple statements

3. Given this Verilog code snippet used in simulation:

reg [3:0] count = 0;
always @(posedge clk) count <= count + 1;

What will be the value of count after 3 rising clock edges?

medium

A. 2

B. 4

C. 3

D. 0

Solution

1. Step 1: Understand non-blocking assignment behavior

   The '<=' operator updates count at the end of the clock cycle, incrementing by 1 each rising edge.

2. Step 2: Count increments after 3 clock edges

   Starting at 0, after 1 edge count=1, after 2 edges count=2, after 3 edges count=3.

3. Final Answer:

   3 -> Option C

4. Quick Check:

   Count increments by 1 each clock edge [OK]

Hint: Count increments by 1 each clock edge, so 3 edges means count=3 [OK]

Common Mistakes:

• Confusing blocking and non-blocking assignments
• Starting count from 1 instead of 0
• Miscounting clock edges

4. Identify the error in this Verilog code intended for synthesis:

module example(input clk, output reg q);
  always @(clk) begin
    q = ~q;
  end
endmodule

medium

A. Using blocking assignment (=) inside always block for sequential logic

B. Missing initial value for q

C. Output q should not be declared as reg

D. Sensitivity list should be posedge or negedge of clk, not clk alone

Solution

1. Step 1: Check sensitivity list for sequential logic

   Sequential logic must use edge-triggered sensitivity like @(posedge clk) or @(negedge clk), not just @(clk).

2. Step 2: Review other options

   Blocking assignment is discouraged but not a syntax error; reg output is correct; initial value is optional for synthesis.

3. Final Answer:

   Sensitivity list should be posedge or negedge of clk, not clk alone -> Option D

4. Quick Check:

   Sequential always block needs edge sensitivity [OK]

Hint: Use posedge/negedge in sensitivity list for sequential logic [OK]

Common Mistakes:

• Using level sensitivity instead of edge sensitivity
• Confusing blocking and non-blocking assignments
• Thinking reg output is invalid

5. You want to design a 2-bit counter in Verilog that counts from 0 to 3 repeatedly. Which statement about simulation vs synthesis is true?

hard

A. Simulation will show the counter values changing over time; synthesis will create flip-flops to store the count

B. Simulation creates hardware components; synthesis only tests the design behavior

C. Both simulation and synthesis produce the same output waveform files

D. Synthesis ignores the counter logic and only synthesizes inputs

Solution

1. Step 1: Understand simulation role for counter

   Simulation runs the counter logic over time and shows how count changes step-by-step.

2. Step 2: Understand synthesis role for counter

   Synthesis converts the counter logic into hardware flip-flops that store the count values physically.

3. Final Answer:

   Simulation will show the counter values changing over time; synthesis will create flip-flops to store the count -> Option A

4. Quick Check:

   Simulation = behavior; synthesis = hardware [OK]

Hint: Simulation shows behavior; synthesis builds hardware components [OK]

Common Mistakes:

• Mixing up roles of simulation and synthesis
• Thinking synthesis produces waveforms
• Believing synthesis ignores logic