Simulation vs synthesis mental model in Verilog - Practice Questions

Challenge - 5 Problems

❓ Predict Output

intermediate

Simulation output of non-blocking assignments

What is the output of the following Verilog simulation code snippet?

Verilog

module test;
  reg a, b;
  initial begin
    a = 0;
    b = 0;
    a <= 1;
    b <= a;
    #1;
    $display("a=%b b=%b", a, b);
  end
endmodule

A a=1 b=1

B a=1 b=0

C a=0 b=0

D a=0 b=1

💡 Hint

Remember that non-blocking assignments update at the end of the time step.

In simulation, non-blocking assignments (<=) schedule updates to happen after all right-hand sides are evaluated. So 'b <= a;' uses the old value of 'a' (which is 0), so b becomes 0, while a becomes 1.

❓ Predict Output

intermediate

Synthesis behavior of blocking assignments

What is the synthesized hardware behavior of this Verilog always block?

Verilog

always @(posedge clk) begin
  a = b;
  c = a;
end

A Two registers: a gets b, c gets new a (b's value)

B Combinational logic only, no registers

C Synthesis error due to blocking assignments

D Two registers: a gets b, c gets a (old value)

💡 Hint

Consider how blocking assignments execute sequentially inside always blocks.

Blocking assignments (=) execute in order. So 'a = b;' updates 'a' immediately, then 'c = a;' uses the new 'a' value. Synthesized hardware will have registers for 'a' and 'c', with 'c' getting the updated 'a' value.

🧠 Conceptual

advanced

Difference between simulation and synthesis for delays

Which statement correctly describes how delays (#) are treated in simulation vs synthesis?

A Delays are ignored in synthesis but affect timing in simulation

B Delays are synthesized as hardware delay elements

C Delays cause synthesis errors

D Delays are converted to clock cycles in synthesis

💡 Hint

Think about what delays mean in real hardware vs simulation.

Delays (#) are simulation-only constructs to model timing. Synthesis tools ignore them because real hardware timing depends on physical properties, not code delays.

❓ Predict Output

advanced

Simulation output with mixed blocking and non-blocking assignments

What is the output of this Verilog simulation code?

Verilog

module test;
  reg x, y;
  initial begin
    x = 0; y = 0;
    x = 1;
    y <= x;
    #1;
    $display("x=%b y=%b", x, y);
  end
endmodule

A x=0 y=1

B x=1 y=0

C x=0 y=0

D x=1 y=1

💡 Hint

Blocking assignments update immediately, non-blocking update later.

The blocking assignment 'x = 1;' updates x immediately to 1. The non-blocking 'y <= x;' schedules y to update after the time step using the current x (which is now 1). So y becomes 1 at display time.

🧠 Conceptual

expert

Why some Verilog constructs simulate but do not synthesize

Which reason best explains why some Verilog code runs in simulation but cannot be synthesized?

A Synthesis requires all variables to be initialized

B Simulation ignores syntax errors that synthesis detects

C Simulation allows behavioral constructs that have no hardware equivalent

D Synthesis tools only accept combinational logic

💡 Hint

Think about the difference between describing behavior and describing hardware.

Simulation can run code that models behavior with constructs like delays, file I/O, or infinite loops, which do not correspond to physical hardware and thus cannot be synthesized.

Practice

1. What is the main purpose of simulation in Verilog?

easy

A. To convert the design into physical hardware

B. To check how the design behaves over time step-by-step

C. To write the final hardware layout

D. To optimize the hardware speed automatically

Solution

1. Step 1: Understand simulation role

   Simulation runs the design in a virtual environment to see how it behaves over time.

2. Step 2: Compare with synthesis role

   Synthesis is about creating hardware, not checking behavior step-by-step.

3. Final Answer:

   To check how the design behaves over time step-by-step -> Option B

4. Quick Check:

   Simulation = behavior check [OK]

Hint: Simulation means testing behavior over time, not hardware creation [OK]

Common Mistakes:

• Confusing synthesis with simulation
• Thinking simulation creates hardware
• Believing simulation optimizes hardware

2. Which of the following is a correct Verilog syntax for a simple always block used in simulation?

easy

A. always @(posedge clk) begin count = count + 1; end

B. always posedge clk { count = count + 1; }

C. always @(clk) count <= count + 1;

D. always #10 count = count + 1

Solution

1. Step 1: Check correct always block syntax

   The correct syntax uses 'always @(posedge clk) begin ... end' with proper parentheses and keywords.

2. Step 2: Identify syntax errors in other options

   always posedge clk { count = count + 1; } uses braces and wrong syntax; C uses wrong sensitivity list; D uses delay but lacks begin-end block.

3. Final Answer:

   always @(posedge clk) begin count = count + 1; end -> Option A

4. Quick Check:

   Correct always block syntax = always @(posedge clk) begin count = count + 1; end [OK]

Hint: Always blocks use @(event) with begin-end for multiple statements [OK]

Common Mistakes:

• Using braces {} instead of begin-end
• Wrong sensitivity list syntax
• Missing begin-end for multiple statements

3. Given this Verilog code snippet used in simulation:

reg [3:0] count = 0;
always @(posedge clk) count <= count + 1;

What will be the value of count after 3 rising clock edges?

medium

A. 2

B. 4

C. 3

D. 0

Solution

1. Step 1: Understand non-blocking assignment behavior

   The '<=' operator updates count at the end of the clock cycle, incrementing by 1 each rising edge.

2. Step 2: Count increments after 3 clock edges

   Starting at 0, after 1 edge count=1, after 2 edges count=2, after 3 edges count=3.

3. Final Answer:

   3 -> Option C

4. Quick Check:

   Count increments by 1 each clock edge [OK]

Hint: Count increments by 1 each clock edge, so 3 edges means count=3 [OK]

Common Mistakes:

• Confusing blocking and non-blocking assignments
• Starting count from 1 instead of 0
• Miscounting clock edges

4. Identify the error in this Verilog code intended for synthesis:

module example(input clk, output reg q);
  always @(clk) begin
    q = ~q;
  end
endmodule

medium

A. Using blocking assignment (=) inside always block for sequential logic

B. Missing initial value for q

C. Output q should not be declared as reg

D. Sensitivity list should be posedge or negedge of clk, not clk alone

Solution

1. Step 1: Check sensitivity list for sequential logic

   Sequential logic must use edge-triggered sensitivity like @(posedge clk) or @(negedge clk), not just @(clk).

2. Step 2: Review other options

   Blocking assignment is discouraged but not a syntax error; reg output is correct; initial value is optional for synthesis.

3. Final Answer:

   Sensitivity list should be posedge or negedge of clk, not clk alone -> Option D

4. Quick Check:

   Sequential always block needs edge sensitivity [OK]

Hint: Use posedge/negedge in sensitivity list for sequential logic [OK]

Common Mistakes:

• Using level sensitivity instead of edge sensitivity
• Confusing blocking and non-blocking assignments
• Thinking reg output is invalid

5. You want to design a 2-bit counter in Verilog that counts from 0 to 3 repeatedly. Which statement about simulation vs synthesis is true?

hard

A. Simulation will show the counter values changing over time; synthesis will create flip-flops to store the count

B. Simulation creates hardware components; synthesis only tests the design behavior

C. Both simulation and synthesis produce the same output waveform files

D. Synthesis ignores the counter logic and only synthesizes inputs

Solution

1. Step 1: Understand simulation role for counter

   Simulation runs the counter logic over time and shows how count changes step-by-step.

2. Step 2: Understand synthesis role for counter

   Synthesis converts the counter logic into hardware flip-flops that store the count values physically.

3. Final Answer:

   Simulation will show the counter values changing over time; synthesis will create flip-flops to store the count -> Option A

4. Quick Check:

   Simulation = behavior; synthesis = hardware [OK]

Hint: Simulation shows behavior; synthesis builds hardware components [OK]

Common Mistakes:

• Mixing up roles of simulation and synthesis
• Thinking synthesis produces waveforms
• Believing synthesis ignores logic