Simulation vs synthesis mental model in Verilog - Hands-On Comparison

Simulation vs Synthesis Mental Model in Verilog

📖 Scenario: You are designing a simple digital circuit using Verilog. You want to understand how your code behaves during simulation and how it will be interpreted during synthesis to hardware.This project will help you see the difference between simulation-only constructs and synthesis-friendly code.

🎯 Goal: Build a Verilog module that uses a simulation-only construct and a synthesis-compatible construct. Then observe the output during simulation and understand what will be synthesized.

📋 What You'll Learn

Create a Verilog module with a register and a wire

Add a simulation-only initial block to set the register

Add a synthesis-compatible always block to update the register

Print the register value during simulation

💡 Why This Matters

🌍 Real World

Understanding the difference between simulation-only code and synthesisable code is crucial when designing digital circuits to ensure your design works correctly in simulation and can be implemented in hardware.

💼 Career

Digital design engineers and FPGA developers must write Verilog code that simulates correctly and synthesizes to hardware. Knowing which constructs are simulation-only helps avoid bugs and synthesis errors.

1

Create the basic Verilog module with a register and a wire

Write a Verilog module named sim_vs_syn with an input clock clk, a register reg_val of 8 bits, and a wire wire_val of 8 bits.

Verilog

module sim_vs_syn(input clk);
  reg [7:0] reg_val;
  wire [7:0] wire_val;
  // Your code here
endmodule

Hint

Define a module with input clk, an 8-bit register reg_val, and an 8-bit wire wire_val.

2

Add a simulation-only initial block to set the register

Add an initial block that sets reg_val to 8'hAA at the start of simulation.

Verilog

module sim_vs_syn(input clk);
  reg [7:0] reg_val;
  wire [7:0] wire_val;

  // Your code here
endmodule

Hint

Use an initial block to assign reg_val the value 8'hAA at simulation start.

3

Add a synthesis-compatible always block to update the register

Add an always @(posedge clk) block that increments reg_val by 1 on each clock rising edge.

Verilog

module sim_vs_syn(input clk);
  reg [7:0] reg_val;
  wire [7:0] wire_val;

  initial begin
    reg_val = 8'hAA;
  end

  // Your code here
endmodule

Hint

Use an always @(posedge clk) block to increment reg_val by 1 on each clock.

4

Print the register value during simulation

Add an always @(posedge clk) block that uses $display to print the current value of reg_val during simulation.

Verilog

module sim_vs_syn(input clk);
  reg [7:0] reg_val;
  wire [7:0] wire_val;

  initial begin
    reg_val = 8'hAA;
  end

  always @(posedge clk) begin
    reg_val <= reg_val + 1;
  end

  // Your code here
endmodule

Hint

Use $display inside an always @(posedge clk) block to print reg_val in hexadecimal.

Practice

1. What is the main purpose of simulation in Verilog?

easy

A. To convert the design into physical hardware

B. To check how the design behaves over time step-by-step

C. To write the final hardware layout

D. To optimize the hardware speed automatically

Solution

1. Step 1: Understand simulation role

   Simulation runs the design in a virtual environment to see how it behaves over time.

2. Step 2: Compare with synthesis role

   Synthesis is about creating hardware, not checking behavior step-by-step.

3. Final Answer:

   To check how the design behaves over time step-by-step -> Option B

4. Quick Check:

   Simulation = behavior check [OK]

Hint: Simulation means testing behavior over time, not hardware creation [OK]

Common Mistakes:

• Confusing synthesis with simulation
• Thinking simulation creates hardware
• Believing simulation optimizes hardware

2. Which of the following is a correct Verilog syntax for a simple always block used in simulation?

easy

A. always @(posedge clk) begin count = count + 1; end

B. always posedge clk { count = count + 1; }

C. always @(clk) count <= count + 1;

D. always #10 count = count + 1

Solution

1. Step 1: Check correct always block syntax

   The correct syntax uses 'always @(posedge clk) begin ... end' with proper parentheses and keywords.

2. Step 2: Identify syntax errors in other options

   always posedge clk { count = count + 1; } uses braces and wrong syntax; C uses wrong sensitivity list; D uses delay but lacks begin-end block.

3. Final Answer:

   always @(posedge clk) begin count = count + 1; end -> Option A

4. Quick Check:

   Correct always block syntax = always @(posedge clk) begin count = count + 1; end [OK]

Hint: Always blocks use @(event) with begin-end for multiple statements [OK]

Common Mistakes:

• Using braces {} instead of begin-end
• Wrong sensitivity list syntax
• Missing begin-end for multiple statements

3. Given this Verilog code snippet used in simulation:

reg [3:0] count = 0;
always @(posedge clk) count <= count + 1;

What will be the value of count after 3 rising clock edges?

medium

A. 2

B. 4

C. 3

D. 0

Solution

1. Step 1: Understand non-blocking assignment behavior

   The '<=' operator updates count at the end of the clock cycle, incrementing by 1 each rising edge.

2. Step 2: Count increments after 3 clock edges

   Starting at 0, after 1 edge count=1, after 2 edges count=2, after 3 edges count=3.

3. Final Answer:

   3 -> Option C

4. Quick Check:

   Count increments by 1 each clock edge [OK]

Hint: Count increments by 1 each clock edge, so 3 edges means count=3 [OK]

Common Mistakes:

• Confusing blocking and non-blocking assignments
• Starting count from 1 instead of 0
• Miscounting clock edges

4. Identify the error in this Verilog code intended for synthesis:

module example(input clk, output reg q);
  always @(clk) begin
    q = ~q;
  end
endmodule

medium

A. Using blocking assignment (=) inside always block for sequential logic

B. Missing initial value for q

C. Output q should not be declared as reg

D. Sensitivity list should be posedge or negedge of clk, not clk alone

Solution

1. Step 1: Check sensitivity list for sequential logic

   Sequential logic must use edge-triggered sensitivity like @(posedge clk) or @(negedge clk), not just @(clk).

2. Step 2: Review other options

   Blocking assignment is discouraged but not a syntax error; reg output is correct; initial value is optional for synthesis.

3. Final Answer:

   Sensitivity list should be posedge or negedge of clk, not clk alone -> Option D

4. Quick Check:

   Sequential always block needs edge sensitivity [OK]

Hint: Use posedge/negedge in sensitivity list for sequential logic [OK]

Common Mistakes:

• Using level sensitivity instead of edge sensitivity
• Confusing blocking and non-blocking assignments
• Thinking reg output is invalid

5. You want to design a 2-bit counter in Verilog that counts from 0 to 3 repeatedly. Which statement about simulation vs synthesis is true?

hard

A. Simulation will show the counter values changing over time; synthesis will create flip-flops to store the count

B. Simulation creates hardware components; synthesis only tests the design behavior

C. Both simulation and synthesis produce the same output waveform files

D. Synthesis ignores the counter logic and only synthesizes inputs

Solution

1. Step 1: Understand simulation role for counter

   Simulation runs the counter logic over time and shows how count changes step-by-step.

2. Step 2: Understand synthesis role for counter

   Synthesis converts the counter logic into hardware flip-flops that store the count values physically.

3. Final Answer:

   Simulation will show the counter values changing over time; synthesis will create flip-flops to store the count -> Option A

4. Quick Check:

   Simulation = behavior; synthesis = hardware [OK]

Hint: Simulation shows behavior; synthesis builds hardware components [OK]

Common Mistakes:

• Mixing up roles of simulation and synthesis
• Thinking synthesis produces waveforms
• Believing synthesis ignores logic