Port declaration (input, output, inout) in Verilog - Step-by-Step Execution

Concept Flow - Port declaration (input, output, inout)

Start module

↓

Declare ports

↓

input

↓

Define direction and width

↓

Use ports in module

↓

End module

The flow shows starting a module, declaring ports as input, output, or inout, defining their widths, then using them inside the module before ending.

Execution Sample

Verilog

module example(
  input wire clk,
  output reg led,
  inout wire data
);

This code declares a module with three ports: an input clock, an output LED signal, and a bidirectional data line.

Execution Table

Step	Port Name	Direction	Type	Width	Action
1	clk	input	wire	1 bit	Declare input port clk as wire
2	led	output	reg	1 bit	Declare output port led as reg
3	data	inout	wire	1 bit	Declare inout port data as wire
4	module body	-	-	-	Use ports inside module logic
5	endmodule	-	-	-	End of module declaration

💡 All ports declared with direction and type; module declaration complete.

Variable Tracker

Port	Initial Declaration	After Step 1	After Step 2	After Step 3	Final
clk	undefined	input wire	input wire	input wire	input wire
led	undefined	undefined	output reg	output reg	output reg
data	undefined	undefined	undefined	inout wire	inout wire

Key Moments - 3 Insights

Why is 'led' declared as 'output reg' instead of 'output wire'?

Because 'led' is assigned inside an always block (sequential logic), it must be declared as 'reg' to hold its value, as shown in execution_table step 2.

What does 'inout' mean for the 'data' port?

'inout' means the port can act as both input and output, allowing bidirectional data flow, as declared in execution_table step 3.

Can input ports be declared as 'reg'?

No, input ports are usually wires because they receive signals from outside; declaring them as 'reg' is not standard, as seen in execution_table step 1.

Visual Quiz - 3 Questions

Look at the execution table, what is the direction and type of the 'clk' port at step 1?

A input wire

B output reg

C inout wire

D input reg

💡 Hint

Check the row for step 1 in the execution_table under Direction and Type columns.

At which step is the 'data' port declared as 'inout wire'?

A Step 2

B Step 3

C Step 1

D Step 4

💡 Hint

Look at the execution_table row for 'data' port and find when 'inout wire' appears.

If 'led' was declared as 'output wire' instead of 'output reg', what would change in the variable_tracker?

A 'led' would be 'input wire'

B 'led' would be undefined

C 'led' would show 'output wire' from step 2 onward

D No change

💡 Hint

Check the variable_tracker row for 'led' and imagine changing its declaration at step 2.

Concept Snapshot

Port declaration syntax:
module name(
  input [type] name,
  output [type] name,
  inout [type] name
);

- input: signal into module (usually wire)
- output: signal out (wire or reg if assigned in always)
- inout: bidirectional signal

Define width if needed, e.g. input [3:0] data;

Full Transcript

This visual execution shows how to declare ports in Verilog modules. First, the module starts, then ports are declared as input, output, or inout with their types and widths. Inputs are usually wires, outputs can be wires or regs depending on usage, and inouts allow two-way signals. The execution table traces each port declaration step by step. The variable tracker shows how each port's declaration state changes. Key moments clarify common confusions like why outputs assigned in always blocks use reg type. The quiz tests understanding of port directions and types at different steps. The snapshot summarizes the syntax and rules for port declarations.

Practice

1. Which keyword in Verilog is used to declare a port that receives signals from outside the module?

easy

A. input

B. output

C. inout

D. wire

Solution

1. Step 1: Understand port directions

   In Verilog, ports can be inputs, outputs, or bidirectional (inout).

2. Step 2: Identify the keyword for receiving signals

   The keyword input is used to declare ports that receive signals from outside the module.

3. Final Answer:

   input -> Option A

4. Quick Check:

   input = receives signals [OK]

Hint: Input ports receive signals from outside [OK]

Common Mistakes:

• Confusing output with input
• Using wire instead of input for ports
• Thinking inout means input only

2. Which of the following is the correct way to declare a 4-bit output port named data_out in Verilog?

easy

A. inout [4:0] data_out;

B. input [3:0] data_out;

C. output [3:0] data_out;

D. output data_out[3:0];

Solution

1. Step 1: Check port direction and width syntax

   Output ports use the keyword output. The width is declared as [3:0] for 4 bits.

2. Step 2: Validate the syntax correctness

   output [3:0] data_out; correctly declares a 4-bit output port as output [3:0] data_out;. output data_out[3:0]; has incorrect syntax placing the width after the name.

3. Final Answer:

   output [3:0] data_out; -> Option C

4. Quick Check:

   output [3:0] name; is correct syntax [OK]

Hint: Declare width before port name with brackets [OK]

Common Mistakes:

• Placing width after port name
• Using input instead of output
• Incorrect bit range like [4:0]

3. Consider this Verilog module header:

module example(input clk, output reg ready, inout wire data);
// module body
endmodule

Which statement about the ports is true?

medium

A. clk is an input port, ready is an output port, data is a bidirectional port

B. clk is an output port, ready is an input port, data is an output port

C. clk is a bidirectional port, ready is an input port, data is an output port

D. All ports are inputs by default

Solution

1. Step 1: Identify each port direction from declaration

   input clk means clk is input, output reg ready means ready is output, and inout wire data means data is bidirectional.

2. Step 2: Match each port with its direction

   clk is an input port, ready is an output port, data is a bidirectional port correctly matches clk as input, ready as output, and data as inout (bidirectional).

3. Final Answer:

   clk is input, ready is output, data is bidirectional -> Option A

4. Quick Check:

   input, output, inout match ports [OK]

Hint: Match keywords input/output/inout to port roles [OK]

Common Mistakes:

• Mixing input and output roles
• Assuming all ports default to input
• Ignoring reg or wire keywords

4. Identify the error in this Verilog port declaration:

module test_module(clk, data_out, inout_signal);
  input wire clk;
  output data_out;
  inout inout_signal
endmodule

medium

A. inout keyword is invalid in port list

B. input wire cannot be used for clk

C. output port must be declared as reg

D. Missing semicolon after inout_signal declaration

Solution

1. Step 1: Check syntax of port declarations

   In this non-ANSI style Verilog module, port names are listed in the header, and directions/types are declared inside the module body. Each declaration must end with a semicolon.

2. Step 2: Identify the specific error

   The declaration inout inout_signal lacks the required semicolon.

3. Final Answer:

   Missing semicolon after inout_signal declaration -> Option D

4. Quick Check:

   Declarations inside module end with semicolon [OK]

Hint: Port declarations inside module end with semicolon [OK]

Common Mistakes:

• Missing semicolons after port declarations
• Thinking output must be reg always
• Believing inout is invalid keyword

5. You want to design a Verilog module with a bidirectional data bus named bus that is 8 bits wide. Which is the correct port declaration and internal signal type to allow reading and writing on bus?

hard

A. input [7:0] bus; reg [7:0] bus_internal;

B. inout [7:0] bus; reg [7:0] bus_internal; assign bus = write_enable ? data_out : 8'bz;

C. output [7:0] bus; wire [7:0] bus_internal;

D. inout [7:0] bus; wire bus_internal; assign bus = write_enable ? data_out : 8'bz;

Solution

1. Step 1: Understand bidirectional port requirements

   Bidirectional ports use inout and require internal signals to store data for output, typically declared as reg for driven values.

2. Step 2: Analyze each option for correctness

   inout [7:0] bus; reg [7:0] bus_internal; assign bus = write_enable ? data_out : 8'bz; correctly declares inout [7:0] bus and uses reg [7:0] bus_internal for internal storage, with an assignment controlling bus output with high impedance when not writing.

3. Final Answer:

   inout [7:0] bus; reg [7:0] bus_internal; assign bus = write_enable ? data_out : 8'bz; -> Option B

4. Quick Check:

   inout with reg internal and tri-state assign [OK]

Hint: Use inout with reg and tri-state assign for bidirectional bus [OK]

Common Mistakes:

• Using wire instead of reg for internal signal
• Declaring bus as input or output only
• Not using tri-state (8'bz) for bus when not driving