Port declaration (input, output, inout) in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this Verilog module port declaration?

Consider the following Verilog module declaration. What is the direction of port data?

Verilog

module example_module(clk, data, reset);
  input clk;
  output [7:0] data;
  input reset;
endmodule

A data is an output port

B data is an input port

C data is an inout port

D data is not declared as a port

💡 Hint

Look at the keyword before the port name in the declaration.

The keyword 'output' before 'data' means it is an output port.

❓ Predict Output

intermediate

What is the width of the input port addr?

Given this Verilog port declaration, what is the width of the input port addr?

Verilog

module mem_access(addr, data_in, data_out);
  input [15:0] addr;
  input [7:0] data_in;
  output [7:0] data_out;
endmodule

A 16 bits

B 8 bits

C 1 bit

D 32 bits

💡 Hint

Check the range inside the square brackets before the port name.

The range [15:0] means the port is 16 bits wide.

❓ Predict Output

advanced

What error does this Verilog port declaration cause?

Examine this Verilog module port declaration. What error will occur?

Verilog

module test_module(
  input wire clk,
  output reg [3:0] out_signal,
  inout wire data_bus
);
endmodule

A SyntaxError: Missing comma between ports

B SyntaxError: Missing semicolon after inout declaration

C TypeError: inout cannot be declared without wire or reg

D No error, valid port declaration

💡 Hint

Observe the commas separating the port declarations in the ANSI-style header.

No error, valid port declaration. In ANSI-style module declarations (Verilog-2001), ports are listed with their directions and optional types/net kinds, separated by commas, without semicolons inside the port list.

❓ Predict Output

advanced

What is the direction and width of bus in this module?

Analyze the port declaration below. What is the direction and bit width of the port bus?

Verilog

module complex_port(
  input wire clk,
  inout [7:0] bus,
  output reg ready
);
endmodule

A bus is an 8-bit output port

B bus is an 8-bit inout port

C bus is an 8-bit input port

D bus is a 1-bit inout port

💡 Hint

Look at the keyword and the range before the port name.

The keyword 'inout' means the port can be input or output, and [7:0] means it is 8 bits wide.

🧠 Conceptual

expert

How many ports are declared in this Verilog module?

Count the total number of ports declared in this Verilog module header.

Verilog

module multi_port(
  input clk,
  input reset,
  output [3:0] status,
  inout [15:0] data_bus
);
endmodule

A 5 ports

B 3 ports

C 4 ports

D 6 ports

💡 Hint

Count each port name listed with its direction keyword.

The ports are clk, reset, status, and data_bus, totaling 4 ports.

Practice

1. Which keyword in Verilog is used to declare a port that receives signals from outside the module?

easy

A. input

B. output

C. inout

D. wire

Solution

1. Step 1: Understand port directions

   In Verilog, ports can be inputs, outputs, or bidirectional (inout).

2. Step 2: Identify the keyword for receiving signals

   The keyword input is used to declare ports that receive signals from outside the module.

3. Final Answer:

   input -> Option A

4. Quick Check:

   input = receives signals [OK]

Hint: Input ports receive signals from outside [OK]

Common Mistakes:

• Confusing output with input
• Using wire instead of input for ports
• Thinking inout means input only

2. Which of the following is the correct way to declare a 4-bit output port named data_out in Verilog?

easy

A. inout [4:0] data_out;

B. input [3:0] data_out;

C. output [3:0] data_out;

D. output data_out[3:0];

Solution

1. Step 1: Check port direction and width syntax

   Output ports use the keyword output. The width is declared as [3:0] for 4 bits.

2. Step 2: Validate the syntax correctness

   output [3:0] data_out; correctly declares a 4-bit output port as output [3:0] data_out;. output data_out[3:0]; has incorrect syntax placing the width after the name.

3. Final Answer:

   output [3:0] data_out; -> Option C

4. Quick Check:

   output [3:0] name; is correct syntax [OK]

Hint: Declare width before port name with brackets [OK]

Common Mistakes:

• Placing width after port name
• Using input instead of output
• Incorrect bit range like [4:0]

3. Consider this Verilog module header:

module example(input clk, output reg ready, inout wire data);
// module body
endmodule

Which statement about the ports is true?

medium

A. clk is an input port, ready is an output port, data is a bidirectional port

B. clk is an output port, ready is an input port, data is an output port

C. clk is a bidirectional port, ready is an input port, data is an output port

D. All ports are inputs by default

Solution

1. Step 1: Identify each port direction from declaration

   input clk means clk is input, output reg ready means ready is output, and inout wire data means data is bidirectional.

2. Step 2: Match each port with its direction

   clk is an input port, ready is an output port, data is a bidirectional port correctly matches clk as input, ready as output, and data as inout (bidirectional).

3. Final Answer:

   clk is input, ready is output, data is bidirectional -> Option A

4. Quick Check:

   input, output, inout match ports [OK]

Hint: Match keywords input/output/inout to port roles [OK]

Common Mistakes:

• Mixing input and output roles
• Assuming all ports default to input
• Ignoring reg or wire keywords

4. Identify the error in this Verilog port declaration:

module test_module(clk, data_out, inout_signal);
  input wire clk;
  output data_out;
  inout inout_signal
endmodule

medium

A. inout keyword is invalid in port list

B. input wire cannot be used for clk

C. output port must be declared as reg

D. Missing semicolon after inout_signal declaration

Solution

1. Step 1: Check syntax of port declarations

   In this non-ANSI style Verilog module, port names are listed in the header, and directions/types are declared inside the module body. Each declaration must end with a semicolon.

2. Step 2: Identify the specific error

   The declaration inout inout_signal lacks the required semicolon.

3. Final Answer:

   Missing semicolon after inout_signal declaration -> Option D

4. Quick Check:

   Declarations inside module end with semicolon [OK]

Hint: Port declarations inside module end with semicolon [OK]

Common Mistakes:

• Missing semicolons after port declarations
• Thinking output must be reg always
• Believing inout is invalid keyword

5. You want to design a Verilog module with a bidirectional data bus named bus that is 8 bits wide. Which is the correct port declaration and internal signal type to allow reading and writing on bus?

hard

A. input [7:0] bus; reg [7:0] bus_internal;

B. inout [7:0] bus; reg [7:0] bus_internal; assign bus = write_enable ? data_out : 8'bz;

C. output [7:0] bus; wire [7:0] bus_internal;

D. inout [7:0] bus; wire bus_internal; assign bus = write_enable ? data_out : 8'bz;

Solution

1. Step 1: Understand bidirectional port requirements

   Bidirectional ports use inout and require internal signals to store data for output, typically declared as reg for driven values.

2. Step 2: Analyze each option for correctness

   inout [7:0] bus; reg [7:0] bus_internal; assign bus = write_enable ? data_out : 8'bz; correctly declares inout [7:0] bus and uses reg [7:0] bus_internal for internal storage, with an assignment controlling bus output with high impedance when not writing.

3. Final Answer:

   inout [7:0] bus; reg [7:0] bus_internal; assign bus = write_enable ? data_out : 8'bz; -> Option B

4. Quick Check:

   inout with reg internal and tri-state assign [OK]

Hint: Use inout with reg and tri-state assign for bidirectional bus [OK]

Common Mistakes:

• Using wire instead of reg for internal signal
• Declaring bus as input or output only
• Not using tri-state (8'bz) for bus when not driving