Port declaration (input, output, inout) in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a 1-bit input port named clk.

Verilog

module example_module([1] clk);
endmodule

Drag options to blanks, or click blank then click option'

Awire

Boutput

Cinout

Dinput

Attempts:

3 left

💡 Hint

Common Mistakes

Using output instead of input for input ports.

Using wire keyword which is not a port direction.

The keyword input declares a port as an input signal to the module.

2fill in blank

medium

Complete the code to declare a 4-bit output port named data_out.

Verilog

module example_module(output [1] [3:0] data_out);
endmodule

Drag options to blanks, or click blank then click option'

Awire

Breg

Cinput

Dinout

Attempts:

3 left

💡 Hint

Common Mistakes

Using reg without a procedural block.

Using input or inout keywords incorrectly.

By default, output ports are wires unless declared as reg. Here, wire is used to declare a 4-bit output port.

3fill in blank

hard

Fix the error in the port declaration to correctly declare a bidirectional port named data_bus.

Verilog

module example_module([1] [7:0] data_bus);
endmodule

Drag options to blanks, or click blank then click option'

Ainput

Binout

Cwire

Doutput

Attempts:

3 left

💡 Hint

Common Mistakes

Using input or output instead of inout for bidirectional ports.

Omitting the port direction keyword.

The inout keyword declares a bidirectional port that can act as input or output.

4fill in blank

hard

Fill both blanks to declare a 2-bit input port named addr and a 1-bit output port named ready.

Verilog

module example_module([1] [1:0] addr, [2] ready);
endmodule

Drag options to blanks, or click blank then click option'

Ainput

Boutput

Cinout

Dwire

Attempts:

3 left

💡 Hint

Common Mistakes

Swapping input and output keywords.

Using inout incorrectly for these ports.

input declares the addr port as input, and output declares ready as output.

5fill in blank

hard

Fill all three blanks to declare a 1-bit input clk, a 1-bit inout data, and a 3-bit output status.

Verilog

module example_module([1] clk, [2] data, [3] [2:0] status);
endmodule

Drag options to blanks, or click blank then click option'

Ainput

Boutput

Cinout

Dwire

Attempts:

3 left

💡 Hint

Common Mistakes

Mixing up port directions.

Using wire instead of direction keywords.

input for clk, inout for bidirectional data, and output for status port.

Practice

1. Which keyword in Verilog is used to declare a port that receives signals from outside the module?

easy

A. input

B. output

C. inout

D. wire

Solution

1. Step 1: Understand port directions

   In Verilog, ports can be inputs, outputs, or bidirectional (inout).

2. Step 2: Identify the keyword for receiving signals

   The keyword input is used to declare ports that receive signals from outside the module.

3. Final Answer:

   input -> Option A

4. Quick Check:

   input = receives signals [OK]

Hint: Input ports receive signals from outside [OK]

Common Mistakes:

• Confusing output with input
• Using wire instead of input for ports
• Thinking inout means input only

2. Which of the following is the correct way to declare a 4-bit output port named data_out in Verilog?

easy

A. inout [4:0] data_out;

B. input [3:0] data_out;

C. output [3:0] data_out;

D. output data_out[3:0];

Solution

1. Step 1: Check port direction and width syntax

   Output ports use the keyword output. The width is declared as [3:0] for 4 bits.

2. Step 2: Validate the syntax correctness

   output [3:0] data_out; correctly declares a 4-bit output port as output [3:0] data_out;. output data_out[3:0]; has incorrect syntax placing the width after the name.

3. Final Answer:

   output [3:0] data_out; -> Option C

4. Quick Check:

   output [3:0] name; is correct syntax [OK]

Hint: Declare width before port name with brackets [OK]

Common Mistakes:

• Placing width after port name
• Using input instead of output
• Incorrect bit range like [4:0]

3. Consider this Verilog module header:

module example(input clk, output reg ready, inout wire data);
// module body
endmodule

Which statement about the ports is true?

medium

A. clk is an input port, ready is an output port, data is a bidirectional port

B. clk is an output port, ready is an input port, data is an output port

C. clk is a bidirectional port, ready is an input port, data is an output port

D. All ports are inputs by default

Solution

1. Step 1: Identify each port direction from declaration

   input clk means clk is input, output reg ready means ready is output, and inout wire data means data is bidirectional.

2. Step 2: Match each port with its direction

   clk is an input port, ready is an output port, data is a bidirectional port correctly matches clk as input, ready as output, and data as inout (bidirectional).

3. Final Answer:

   clk is input, ready is output, data is bidirectional -> Option A

4. Quick Check:

   input, output, inout match ports [OK]

Hint: Match keywords input/output/inout to port roles [OK]

Common Mistakes:

• Mixing input and output roles
• Assuming all ports default to input
• Ignoring reg or wire keywords

4. Identify the error in this Verilog port declaration:

module test_module(clk, data_out, inout_signal);
  input wire clk;
  output data_out;
  inout inout_signal
endmodule

medium

A. inout keyword is invalid in port list

B. input wire cannot be used for clk

C. output port must be declared as reg

D. Missing semicolon after inout_signal declaration

Solution

1. Step 1: Check syntax of port declarations

   In this non-ANSI style Verilog module, port names are listed in the header, and directions/types are declared inside the module body. Each declaration must end with a semicolon.

2. Step 2: Identify the specific error

   The declaration inout inout_signal lacks the required semicolon.

3. Final Answer:

   Missing semicolon after inout_signal declaration -> Option D

4. Quick Check:

   Declarations inside module end with semicolon [OK]

Hint: Port declarations inside module end with semicolon [OK]

Common Mistakes:

• Missing semicolons after port declarations
• Thinking output must be reg always
• Believing inout is invalid keyword

5. You want to design a Verilog module with a bidirectional data bus named bus that is 8 bits wide. Which is the correct port declaration and internal signal type to allow reading and writing on bus?

hard

A. input [7:0] bus; reg [7:0] bus_internal;

B. inout [7:0] bus; reg [7:0] bus_internal; assign bus = write_enable ? data_out : 8'bz;

C. output [7:0] bus; wire [7:0] bus_internal;

D. inout [7:0] bus; wire bus_internal; assign bus = write_enable ? data_out : 8'bz;

Solution

1. Step 1: Understand bidirectional port requirements

   Bidirectional ports use inout and require internal signals to store data for output, typically declared as reg for driven values.

2. Step 2: Analyze each option for correctness

   inout [7:0] bus; reg [7:0] bus_internal; assign bus = write_enable ? data_out : 8'bz; correctly declares inout [7:0] bus and uses reg [7:0] bus_internal for internal storage, with an assignment controlling bus output with high impedance when not writing.

3. Final Answer:

   inout [7:0] bus; reg [7:0] bus_internal; assign bus = write_enable ? data_out : 8'bz; -> Option B

4. Quick Check:

   inout with reg internal and tri-state assign [OK]

Hint: Use inout with reg and tri-state assign for bidirectional bus [OK]

Common Mistakes:

• Using wire instead of reg for internal signal
• Declaring bus as input or output only
• Not using tri-state (8'bz) for bus when not driving