Multiplexer design in Verilog - Step-by-Step Execution

Concept Flow - Multiplexer design

Inputs: data lines, select lines

↓

Check select lines value

↓

Select corresponding data input

↓

Output selected data

↓

END

The multiplexer takes multiple data inputs and uses select lines to choose which input to send to the output.

Execution Sample

Verilog

module mux2to1(
  input wire a, b,
  input wire sel,
  output wire y
);
  assign y = sel ? b : a;
endmodule

This 2-to-1 multiplexer outputs 'a' or 'b' based on the select line 'sel'.

Execution Table

Step	sel	a	b	Condition (sel ? b : a)	Output y
1	0	0	0	sel=0, output a=0	0
2	0	1	0	sel=0, output a=1	1
3	1	0	1	sel=1, output b=1	1
4	1	1	1	sel=1, output b=1	1
5	0	1	1	sel=0, output a=1	1
Exit	-	-	-	No more inputs to test	-

💡 Sample input combinations tested, execution ends.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	Final
sel	-	0	0	1	1	0	-
a	-	0	1	0	1	1	-
b	-	0	0	1	1	1	-
y	-	0	1	1	1	1	-

Key Moments - 2 Insights

Why does the output y change when sel changes?

Because the output y depends on sel: if sel=0, y outputs a; if sel=1, y outputs b, as shown in execution_table rows 1 and 3.

What happens if both inputs a and b are 1 but sel is 0?

Output y will be a (which is 1), as shown in execution_table row 5, because sel=0 selects input a.

Visual Quiz - 3 Questions

Look at the execution table, what is the output y when sel=1, a=0, b=1?

A 0

B 1

C Undefined

D Depends on previous state

💡 Hint

Check execution_table row 3 where sel=1, a=0, b=1 and output y=1.

At which step does the output y equal input a even though input b is 1?

A Step 5

B Step 3

C Step 4

D Step 2

💡 Hint

Look at execution_table row 5 where sel=0 selects a=1 despite b=1.

If sel is always 0, what will be the output y for inputs a=1, b=0?

A 0

B Depends on b

C 1

D Toggle between 0 and 1

💡 Hint

Refer to variable_tracker for sel=0 and a=1, output y matches a.

Concept Snapshot

Multiplexer (mux) selects one input from many based on select lines.
Syntax: assign y = sel ? b : a; for 2-to-1 mux.
If sel=0, output is a; if sel=1, output is b.
Used to route signals efficiently.
Simple conditional assignment controls output.

Full Transcript

A multiplexer chooses one input to send to output based on select lines. In the example, a 2-to-1 mux outputs input 'a' if select line 'sel' is 0, or input 'b' if 'sel' is 1. The execution table shows different input combinations and the resulting output. Variables 'sel', 'a', 'b', and 'y' change values step by step. Key moments clarify why output depends on 'sel' and how inputs affect output. The quiz tests understanding of output for given inputs and select values. The snapshot summarizes the mux behavior and syntax.

Practice

1. What is the main purpose of a multiplexer in Verilog design?

easy

A. To select one input from multiple inputs based on selector signals

B. To store data temporarily

C. To perform arithmetic operations

D. To generate clock signals

Solution

1. Step 1: Understand the function of a multiplexer

   A multiplexer routes one of many inputs to a single output based on selector signals.

2. Step 2: Compare with other options

   Other options describe functions unrelated to multiplexers, like storage or arithmetic.

3. Final Answer:

   To select one input from multiple inputs based on selector signals -> Option A

4. Quick Check:

   Multiplexer = Select input [OK]

Hint: Multiplexer chooses one input out of many [OK]

Common Mistakes:

• Confusing multiplexer with memory elements
• Thinking it performs calculations
• Mixing it up with clock generators

2. Which of the following is the correct syntax to define a 2-to-1 multiplexer using a conditional operator in Verilog?

easy

A. assign out = in0 ? sel : in1;

B. assign out = sel & in1 | in0;

C. assign out = sel ? in1 : in0;

D. assign out = sel | in1 & in0;

Solution

1. Step 1: Recall conditional operator syntax

   The conditional operator in Verilog is: condition ? true_value : false_value.

2. Step 2: Match syntax to multiplexer logic

   For a 2-to-1 mux, output is in1 if sel=1, else in0. So, assign out = sel ? in1 : in0; is correct.

3. Final Answer:

   assign out = sel ? in1 : in0; -> Option C

4. Quick Check:

   Conditional operator = condition ? true : false [OK]

Hint: Use condition ? true_val : false_val for mux [OK]

Common Mistakes:

• Using bitwise operators instead of conditional
• Swapping true and false values
• Incorrect operator precedence

3. What is the output of this Verilog code snippet for a 4-to-1 multiplexer when sel = 2'b10 and inputs are in0=0, in1=1, in2=1, in3=0?

module mux4to1(output reg out, input [1:0] sel, input in0, in1, in2, in3);
  always @(*) begin
    case(sel)
      2'b00: out = in0;
      2'b01: out = in1;
      2'b10: out = in2;
      2'b11: out = in3;
    endcase
  end
endmodule

medium

A. 0

B. Error

C. Undefined

D. 1

Solution

1. Step 1: Identify selected input based on sel

   sel = 2'b10 selects input in2 according to the case statement.

2. Step 2: Check value of in2

   in2 is given as 1, so output out = 1.

3. Final Answer:

   1 -> Option D

4. Quick Check:

   sel=2'b10 selects in2=1 [OK]

Hint: Match sel bits to input index [OK]

Common Mistakes:

• Confusing binary selector values
• Ignoring case statement mapping
• Assuming default output without case

4. Identify the error in this Verilog 2-to-1 multiplexer code:

module mux2to1(output reg out, input sel, input in0, in1);
  always @(*) begin
    if (sel == 1) out = in1;
    else if (sel == 0) out = in0;
    else out = 1'bx;
  end
endmodule

medium

A. Using 'else if' instead of 'else' for sel check

B. No default case needed for 1-bit sel

C. Output should be wire, not reg

D. Missing sensitivity list in always block

Solution

1. Step 1: Analyze selector signal type

   sel is 1-bit, so it can only be 0 or 1, no other values possible.

2. Step 2: Check necessity of default case

   Since sel cannot be other than 0 or 1, the 'else out = 1'bx;' is unnecessary.

3. Final Answer:

   No default case needed for 1-bit sel -> Option B

4. Quick Check:

   1-bit sel only 0 or 1, no default needed [OK]

Hint: 1-bit selector has only two values [OK]

Common Mistakes:

• Adding unreachable default cases
• Confusing reg and wire for outputs
• Forgetting sensitivity list is @(*)

5. You need to design an 8-to-1 multiplexer in Verilog using a case statement. Which of the following code snippets correctly implements this multiplexer assuming inputs in0 to in7, selector sel[2:0], and output out?

hard

A. always @(*) begin
case(sel)
3'b000: out = in0;
3'b001: out = in1;
3'b010: out = in2;
3'b011: out = in3;
3'b100: out = in4;
3'b101: out = in5;
3'b110: out = in6;
3'b111: out = in7;
default: out = 1'b0;
endcase
end

B. always @(sel) begin
if(sel == 0) out = in0;
else if(sel == 1) out = in1;
else if(sel == 2) out = in2;
else if(sel == 3) out = in3;
else if(sel == 4) out = in4;
else if(sel == 5) out = in5;
else if(sel == 6) out = in6;
else if(sel == 7) out = in7;
end

C. always @(*) begin
case(sel)
3'b000: out = in7;
3'b001: out = in6;
3'b010: out = in5;
3'b011: out = in4;
3'b100: out = in3;
3'b101: out = in2;
3'b110: out = in1;
3'b111: out = in0;
endcase
end

D. always @(*) begin
case(sel)
3'b000: out = in0;
3'b001: out = in1;
3'b010: out = in2;
3'b011: out = in3;
3'b100: out = in4;
3'b101: out = in5;
3'b110: out = in6;
endcase
end

Solution

1. Step 1: Check completeness of case statement

   always @(*) begin case(sel) 3'b000: out = in0; 3'b001: out = in1; 3'b010: out = in2; 3'b011: out = in3; 3'b100: out = in4; 3'b101: out = in5; 3'b110: out = in6; 3'b111: out = in7; default: out = 1'b0; endcase end covers all 8 selector values (0 to 7) and includes a default case.

2. Step 2: Verify correct input mapping

   always @(*) begin case(sel) 3'b000: out = in0; 3'b001: out = in1; 3'b010: out = in2; 3'b011: out = in3; 3'b100: out = in4; 3'b101: out = in5; 3'b110: out = in6; 3'b111: out = in7; default: out = 1'b0; endcase end maps sel values 3'b000 to 3'b111 to in0 through in7 respectively, which is correct.

3. Step 3: Identify issues in other options

   always @(sel) begin if(sel == 0) out = in0; else if(sel == 1) out = in1; else if(sel == 2) out = in2; else if(sel == 3) out = in3; else if(sel == 4) out = in4; else if(sel == 5) out = in5; else if(sel == 6) out = in6; else if(sel == 7) out = in7; end uses if-else but sensitivity list is only sel, which is acceptable but lacks default. always @(*) begin case(sel) 3'b000: out = in7; 3'b001: out = in6; 3'b010: out = in5; 3'b011: out = in4; 3'b100: out = in3; 3'b101: out = in2; 3'b110: out = in1; 3'b111: out = in0; endcase end reverses input mapping incorrectly. always @(*) begin case(sel) 3'b000: out = in0; 3'b001: out = in1; 3'b010: out = in2; 3'b011: out = in3; 3'b100: out = in4; 3'b101: out = in5; 3'b110: out = in6; endcase end misses case for 3'b111.

4. Final Answer:

   Option A correctly implements 8-to-1 mux with case and default -> Option A

5. Quick Check:

   Complete case with all inputs mapped = always @(*) begin case(sel) 3'b000: out = in0; 3'b001: out = in1; 3'b010: out = in2; 3'b011: out = in3; 3'b100: out = in4; 3'b101: out = in5; 3'b110: out = in6; 3'b111: out = in7; default: out = 1'b0; endcase end [OK]

Hint: Cover all selector values with case and default [OK]

Common Mistakes:

• Missing cases for some selector values
• Incorrect input to selector mapping
• No default case in case statement