Multiplexer design in Verilog - Mini Project: Build & Apply

Multiplexer Design in Verilog

📖 Scenario: You are designing a simple digital circuit called a multiplexer (mux). A multiplexer selects one input from many inputs and sends it to the output based on a selector signal. This is like a railway switch that directs a train to one track out of many.

🎯 Goal: Build a 4-to-1 multiplexer in Verilog. You will create the input signals, define the selector, write the logic to choose the correct input based on the selector, and finally display the output.

📋 What You'll Learn

Create 4 input signals named in0, in1, in2, and in3 with exact values

Create a 2-bit selector signal named sel

Write the multiplexer logic using a case statement on sel

Print the output signal named out

💡 Why This Matters

🌍 Real World

Multiplexers are used in digital electronics to route signals efficiently, saving hardware resources.

💼 Career

Understanding multiplexers is essential for hardware design engineers and FPGA developers who build digital circuits.

1

DATA SETUP: Define the input signals

Create 4 input signals named in0, in1, in2, and in3 as 1-bit registers with values 0, 1, 0, and 1 respectively.

Verilog

// Define 4 input signals with given values
// Your code here

Hint

Use reg to define 1-bit signals and assign the exact values.

2

CONFIGURATION: Define the selector signal

Create a 2-bit register named sel and set it to 2'b10 (binary 2).

Verilog

reg in0 = 0;
reg in1 = 1;
reg in2 = 0;
reg in3 = 1;
// Define 2-bit selector signal sel with value 2'b10
// Your code here

Hint

Use reg [1:0] to define a 2-bit register and assign the binary value 2'b10.

3

CORE LOGIC: Write the multiplexer logic

Create a 1-bit register named out. Use a case statement on sel to assign out the value of in0, in1, in2, or in3 for selector values 2'b00, 2'b01, 2'b10, and 2'b11 respectively.

Verilog

reg in0 = 0;
reg in1 = 1;
reg in2 = 0;
reg in3 = 1;
reg [1:0] sel = 2'b10;
// Define output register out
// Use case on sel to assign out from in0, in1, in2, in3
// Your code here

Hint

Use an always @(*) block with a case statement to assign out based on sel.

4

OUTPUT: Display the output value

Write an initial block that uses $display to print the value of out.

Verilog

reg in0 = 0;
reg in1 = 1;
reg in2 = 0;
reg in3 = 1;
reg [1:0] sel = 2'b10;
reg out;

always @(*) begin
    case(sel)
        2'b00: out = in0;
        2'b01: out = in1;
        2'b10: out = in2;
        2'b11: out = in3;
        default: out = 0;
    endcase
end

// Print the output value using $display
// Your code here

Hint

Use initial block and $display to show the output value.

Practice

1. What is the main purpose of a multiplexer in Verilog design?

easy

A. To select one input from multiple inputs based on selector signals

B. To store data temporarily

C. To perform arithmetic operations

D. To generate clock signals

Solution

1. Step 1: Understand the function of a multiplexer

   A multiplexer routes one of many inputs to a single output based on selector signals.

2. Step 2: Compare with other options

   Other options describe functions unrelated to multiplexers, like storage or arithmetic.

3. Final Answer:

   To select one input from multiple inputs based on selector signals -> Option A

4. Quick Check:

   Multiplexer = Select input [OK]

Hint: Multiplexer chooses one input out of many [OK]

Common Mistakes:

• Confusing multiplexer with memory elements
• Thinking it performs calculations
• Mixing it up with clock generators

2. Which of the following is the correct syntax to define a 2-to-1 multiplexer using a conditional operator in Verilog?

easy

A. assign out = in0 ? sel : in1;

B. assign out = sel & in1 | in0;

C. assign out = sel ? in1 : in0;

D. assign out = sel | in1 & in0;

Solution

1. Step 1: Recall conditional operator syntax

   The conditional operator in Verilog is: condition ? true_value : false_value.

2. Step 2: Match syntax to multiplexer logic

   For a 2-to-1 mux, output is in1 if sel=1, else in0. So, assign out = sel ? in1 : in0; is correct.

3. Final Answer:

   assign out = sel ? in1 : in0; -> Option C

4. Quick Check:

   Conditional operator = condition ? true : false [OK]

Hint: Use condition ? true_val : false_val for mux [OK]

Common Mistakes:

• Using bitwise operators instead of conditional
• Swapping true and false values
• Incorrect operator precedence

3. What is the output of this Verilog code snippet for a 4-to-1 multiplexer when sel = 2'b10 and inputs are in0=0, in1=1, in2=1, in3=0?

module mux4to1(output reg out, input [1:0] sel, input in0, in1, in2, in3);
  always @(*) begin
    case(sel)
      2'b00: out = in0;
      2'b01: out = in1;
      2'b10: out = in2;
      2'b11: out = in3;
    endcase
  end
endmodule

medium

A. 0

B. Error

C. Undefined

D. 1

Solution

1. Step 1: Identify selected input based on sel

   sel = 2'b10 selects input in2 according to the case statement.

2. Step 2: Check value of in2

   in2 is given as 1, so output out = 1.

3. Final Answer:

   1 -> Option D

4. Quick Check:

   sel=2'b10 selects in2=1 [OK]

Hint: Match sel bits to input index [OK]

Common Mistakes:

• Confusing binary selector values
• Ignoring case statement mapping
• Assuming default output without case

4. Identify the error in this Verilog 2-to-1 multiplexer code:

module mux2to1(output reg out, input sel, input in0, in1);
  always @(*) begin
    if (sel == 1) out = in1;
    else if (sel == 0) out = in0;
    else out = 1'bx;
  end
endmodule

medium

A. Using 'else if' instead of 'else' for sel check

B. No default case needed for 1-bit sel

C. Output should be wire, not reg

D. Missing sensitivity list in always block

Solution

1. Step 1: Analyze selector signal type

   sel is 1-bit, so it can only be 0 or 1, no other values possible.

2. Step 2: Check necessity of default case

   Since sel cannot be other than 0 or 1, the 'else out = 1'bx;' is unnecessary.

3. Final Answer:

   No default case needed for 1-bit sel -> Option B

4. Quick Check:

   1-bit sel only 0 or 1, no default needed [OK]

Hint: 1-bit selector has only two values [OK]

Common Mistakes:

• Adding unreachable default cases
• Confusing reg and wire for outputs
• Forgetting sensitivity list is @(*)

5. You need to design an 8-to-1 multiplexer in Verilog using a case statement. Which of the following code snippets correctly implements this multiplexer assuming inputs in0 to in7, selector sel[2:0], and output out?

hard

A. always @(*) begin
case(sel)
3'b000: out = in0;
3'b001: out = in1;
3'b010: out = in2;
3'b011: out = in3;
3'b100: out = in4;
3'b101: out = in5;
3'b110: out = in6;
3'b111: out = in7;
default: out = 1'b0;
endcase
end

B. always @(sel) begin
if(sel == 0) out = in0;
else if(sel == 1) out = in1;
else if(sel == 2) out = in2;
else if(sel == 3) out = in3;
else if(sel == 4) out = in4;
else if(sel == 5) out = in5;
else if(sel == 6) out = in6;
else if(sel == 7) out = in7;
end

C. always @(*) begin
case(sel)
3'b000: out = in7;
3'b001: out = in6;
3'b010: out = in5;
3'b011: out = in4;
3'b100: out = in3;
3'b101: out = in2;
3'b110: out = in1;
3'b111: out = in0;
endcase
end

D. always @(*) begin
case(sel)
3'b000: out = in0;
3'b001: out = in1;
3'b010: out = in2;
3'b011: out = in3;
3'b100: out = in4;
3'b101: out = in5;
3'b110: out = in6;
endcase
end

Solution

1. Step 1: Check completeness of case statement

   always @(*) begin case(sel) 3'b000: out = in0; 3'b001: out = in1; 3'b010: out = in2; 3'b011: out = in3; 3'b100: out = in4; 3'b101: out = in5; 3'b110: out = in6; 3'b111: out = in7; default: out = 1'b0; endcase end covers all 8 selector values (0 to 7) and includes a default case.

2. Step 2: Verify correct input mapping

   always @(*) begin case(sel) 3'b000: out = in0; 3'b001: out = in1; 3'b010: out = in2; 3'b011: out = in3; 3'b100: out = in4; 3'b101: out = in5; 3'b110: out = in6; 3'b111: out = in7; default: out = 1'b0; endcase end maps sel values 3'b000 to 3'b111 to in0 through in7 respectively, which is correct.

3. Step 3: Identify issues in other options

   always @(sel) begin if(sel == 0) out = in0; else if(sel == 1) out = in1; else if(sel == 2) out = in2; else if(sel == 3) out = in3; else if(sel == 4) out = in4; else if(sel == 5) out = in5; else if(sel == 6) out = in6; else if(sel == 7) out = in7; end uses if-else but sensitivity list is only sel, which is acceptable but lacks default. always @(*) begin case(sel) 3'b000: out = in7; 3'b001: out = in6; 3'b010: out = in5; 3'b011: out = in4; 3'b100: out = in3; 3'b101: out = in2; 3'b110: out = in1; 3'b111: out = in0; endcase end reverses input mapping incorrectly. always @(*) begin case(sel) 3'b000: out = in0; 3'b001: out = in1; 3'b010: out = in2; 3'b011: out = in3; 3'b100: out = in4; 3'b101: out = in5; 3'b110: out = in6; endcase end misses case for 3'b111.

4. Final Answer:

   Option A correctly implements 8-to-1 mux with case and default -> Option A

5. Quick Check:

   Complete case with all inputs mapped = always @(*) begin case(sel) 3'b000: out = in0; 3'b001: out = in1; 3'b010: out = in2; 3'b011: out = in3; 3'b100: out = in4; 3'b101: out = in5; 3'b110: out = in6; 3'b111: out = in7; default: out = 1'b0; endcase end [OK]

Hint: Cover all selector values with case and default [OK]

Common Mistakes:

• Missing cases for some selector values
• Incorrect input to selector mapping
• No default case in case statement