Logical operators in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What does the logical AND operator (&&) do in Verilog?

The logical AND operator (&&) returns 1 (true) if both operands are non-zero (true). Otherwise, it returns 0 (false). It is used to combine two conditions.

beginner

Explain the logical OR operator (||) in Verilog.

The logical OR operator (||) returns 1 (true) if at least one of the operands is non-zero (true). It returns 0 only if both operands are zero (false).

beginner

What is the purpose of the logical NOT operator (!) in Verilog?

The logical NOT operator (!) inverts the truth value of its operand. If the operand is non-zero (true), it returns 0 (false). If the operand is zero (false), it returns 1 (true).

intermediate

How do logical operators differ from bitwise operators in Verilog?

Logical operators (&&, ||, !) work on the truth value of entire expressions (true or false). Bitwise operators (&, |, ~) work on each bit of the operands individually.

beginner

What is the result of the expression: (a && b) if a = 1 and b = 0 in Verilog?

The result is 0 because logical AND (&&) returns true only if both a and b are true (non-zero). Since b is 0 (false), the expression is false (0).

Which operator returns true if at least one operand is true in Verilog?

A || (logical OR)

B && (logical AND)

C ! (logical NOT)

D & (bitwise AND)

The logical OR operator (||) returns true if any operand is true.

What does the expression '!0' evaluate to in Verilog?

A 0

B 1

C Undefined

D Error

Logical NOT (!) inverts 0 (false) to 1 (true).

If a = 1 and b = 1, what is the result of 'a && b' in Verilog?

A 0

B b

C a

D 1

Logical AND returns 1 only if both operands are true (non-zero).

Which operator works on each bit individually rather than the whole expression in Verilog?

A &

B ||

C !

D &&

The bitwise AND (&) operates on each bit of the operands.

What is the result of '!(a || b)' if a=0 and b=0 in Verilog?

A a

B 0

C 1

D b

Since both a and b are 0, 'a || b' is 0, so '!' inverts it to 1.

Describe how logical AND, OR, and NOT operators work in Verilog with simple examples.

Think about true/false as 1/0 and how these operators combine or invert them.

Explain the difference between logical operators and bitwise operators in Verilog.

Consider how you check if a whole condition is true vs. manipulating bits.

Practice

1. Which logical operator in Verilog returns true only if both operands are true?

easy

A. ^ (XOR)

B. || (OR)

C. ! (NOT)

D. && (AND)

Solution

1. Step 1: Understand the AND operator

   The AND operator (&&) returns true only when both inputs are true.

2. Step 2: Compare with other operators

   OR (||) returns true if at least one input is true, NOT (!) inverts the input, XOR (^) returns true if inputs differ.

3. Final Answer:

   && (AND) -> Option D

4. Quick Check:

   AND needs both true = && [OK]

Hint: AND needs both true inputs to be true [OK]

Common Mistakes:

• Confusing OR (||) with AND (&&)
• Thinking NOT (!) is a binary operator
• Mixing XOR (^) with AND (&&)

2. Which of the following is the correct syntax for the logical OR operator in Verilog?

easy

A. |

B. ||

C. &

D. &&

Solution

1. Step 1: Identify logical OR syntax

   Logical OR in Verilog is represented by double vertical bars: ||.

2. Step 2: Differentiate from bitwise OR

   Single | is bitwise OR, && is logical AND, & is bitwise AND.

3. Final Answer:

   || -> Option B

4. Quick Check:

   Logical OR = || [OK]

Hint: Logical OR uses double vertical bars || [OK]

Common Mistakes:

• Using single | instead of || for logical OR
• Confusing bitwise and logical operators
• Using && instead of ||

3. What is the output of this Verilog expression if a = 1'b0 and b = 1'b1?
assign result = !(a && b) || a;

medium

A. 1'b0

B. Z (high impedance)

C. 1'b1

D. X (unknown)

Solution

1. Step 1: Evaluate inner AND (a && b)

   a = 0, b = 1, so a && b = 0 (false).

2. Step 2: Apply NOT and OR

   !(0) = 1, then 1 || 0 = 1 (true).

3. Final Answer:

   1'b1 -> Option C

4. Quick Check:

   !(0) || 0 = 1 [OK]

Hint: Evaluate inner && first, then apply ! and || [OK]

Common Mistakes:

• Forgetting NOT (!) flips the value
• Evaluating OR before AND
• Confusing 1'b0 and 1'b1 values

4. Identify the error in this Verilog code snippet:

wire a, b, c;
assign c = a &| b;

medium

A. Incorrect use of &| operator

B. Missing semicolon after wire declaration

C. Using assign instead of always block

D. No error, code is correct

Solution

1. Step 1: Check operator syntax

   The operator &| does not exist in Verilog; bitwise AND is & and bitwise OR is |.

2. Step 2: Confirm correct operator usage

   To combine signals logically, use && or ||; for bitwise, use & or | separately.

3. Final Answer:

   Incorrect use of &| operator -> Option A

4. Quick Check:

   No &| operator in Verilog [OK]

Hint: Check operator symbols carefully; &| is invalid [OK]

Common Mistakes:

• Assuming &| is a valid operator
• Ignoring operator precedence
• Confusing bitwise and logical operators

5. Given inputs a, b, and c, which Verilog expression correctly implements the logic: "Output is true if either a and b are both true, or c is false"?

hard

A. assign out = (a && b) || !c;

B. assign out = !(a && b) || c;

C. assign out = (a || b) && !c;

D. assign out = !(a || b) && c;

Solution

1. Step 1: Translate the condition to logic

   Output is true if (a AND b) is true OR c is false (NOT c).

2. Step 2: Match expression with condition

   assign out = (a && b) || !c; uses (a && b) || !c which matches the condition exactly.

3. Final Answer:

   assign out = (a && b) || !c; -> Option A

4. Quick Check:

   AND + OR + NOT combined correctly [OK]

Hint: Translate words to (a && b) || !c quickly [OK]

Common Mistakes:

• Mixing OR and AND order
• Forgetting to negate c
• Using bitwise instead of logical operators