Logical operators in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of logical AND and OR in Verilog

What is the output of the following Verilog code snippet when a = 1'b1 and b = 1'b0?

Verilog

module test;
  reg a, b;
  wire and_out, or_out;
  assign and_out = a && b;
  assign or_out = a || b;
  initial begin
    a = 1'b1;
    b = 1'b0;
    #1;
    $display("and_out = %b, or_out = %b", and_out, or_out);
  end
endmodule

A and_out = 0, or_out = 1

B and_out = 1, or_out = 1

C and_out = 1, or_out = 0

D and_out = 0, or_out = 0

💡 Hint

Remember that logical AND (&&) is true only if both inputs are true, logical OR (||) is true if at least one input is true.

Since a=1 and b=0, a && b is 0 (false), and a || b is 1 (true).

❓ Predict Output

intermediate

Logical NOT operator behavior

What is the output of the following Verilog code snippet when x = 1'b0?

Verilog

module test;
  reg x;
  wire not_x;
  assign not_x = !x;
  initial begin
    x = 1'b0;
    #1;
    $display("not_x = %b", not_x);
  end
endmodule

A not_x = 1

B not_x = 0

C not_x = x

D not_x = x + 1

💡 Hint

Logical NOT (!) inverts the input bit.

Since x=0, !x is 1.

❓ Predict Output

advanced

Difference between bitwise and logical operators

What is the output of this Verilog code snippet when a = 1'b1 and b = 1'b0?

Verilog

module test;
  reg a, b;
  wire bitwise_and, logical_and;
  assign bitwise_and = a & b;
  assign logical_and = a && b;
  initial begin
    a = 1'b1;
    b = 1'b0;
    #1;
    $display("bitwise_and = %b, logical_and = %b", bitwise_and, logical_and);
  end
endmodule

A bitwise_and = 0, logical_and = 1

B bitwise_and = 1, logical_and = 0

C bitwise_and = 1, logical_and = 1

D bitwise_and = 0, logical_and = 0

💡 Hint

Bitwise AND (&) operates bit by bit; logical AND (&&) treats inputs as boolean values.

a & b = 1 & 0 = 0; a && b = true && false = false (0). Both outputs are 0.

🔧 Debug

advanced

Identify the error in logical operator usage

What error does the following Verilog code produce?

Verilog

module test;
  reg a, b;
  wire result;
  assign result = a &&& b;
endmodule

A TypeError: operands must be single bits

B No error, result is assigned correctly

C SyntaxError: unexpected token '&&&'

D RuntimeError: invalid logical operation

💡 Hint

Check the operator symbols carefully; '&&&' is not a valid Verilog operator.

'&&&' is not a valid operator in Verilog, causing a syntax error.

🚀 Application

expert

Evaluate complex logical expression output

Given the following Verilog code, what is the value of 'out' after execution when a=1'b1, b=1'b0, c=1'b1?

Verilog

module test;
  reg a, b, c;
  wire out;
  assign out = (a || b) && (!c || b);
  initial begin
    a = 1'b1;
    b = 1'b0;
    c = 1'b1;
    #1;
    $display("out = %b", out);
  end
endmodule

A out = z (high impedance)

B out = 0

C out = x (unknown)

D out = 1

💡 Hint

Evaluate each part step-by-step: (a || b), (!c || b), then combine with &&.

a || b = 1 || 0 = 1; !c || b = !1 || 0 = 0 || 0 = 0; so out = 1 && 0 = 0.

Practice

1. Which logical operator in Verilog returns true only if both operands are true?

easy

A. ^ (XOR)

B. || (OR)

C. ! (NOT)

D. && (AND)

Solution

1. Step 1: Understand the AND operator

   The AND operator (&&) returns true only when both inputs are true.

2. Step 2: Compare with other operators

   OR (||) returns true if at least one input is true, NOT (!) inverts the input, XOR (^) returns true if inputs differ.

3. Final Answer:

   && (AND) -> Option D

4. Quick Check:

   AND needs both true = && [OK]

Hint: AND needs both true inputs to be true [OK]

Common Mistakes:

• Confusing OR (||) with AND (&&)
• Thinking NOT (!) is a binary operator
• Mixing XOR (^) with AND (&&)

2. Which of the following is the correct syntax for the logical OR operator in Verilog?

easy

A. |

B. ||

C. &

D. &&

Solution

1. Step 1: Identify logical OR syntax

   Logical OR in Verilog is represented by double vertical bars: ||.

2. Step 2: Differentiate from bitwise OR

   Single | is bitwise OR, && is logical AND, & is bitwise AND.

3. Final Answer:

   || -> Option B

4. Quick Check:

   Logical OR = || [OK]

Hint: Logical OR uses double vertical bars || [OK]

Common Mistakes:

• Using single | instead of || for logical OR
• Confusing bitwise and logical operators
• Using && instead of ||

3. What is the output of this Verilog expression if a = 1'b0 and b = 1'b1?
assign result = !(a && b) || a;

medium

A. 1'b0

B. Z (high impedance)

C. 1'b1

D. X (unknown)

Solution

1. Step 1: Evaluate inner AND (a && b)

   a = 0, b = 1, so a && b = 0 (false).

2. Step 2: Apply NOT and OR

   !(0) = 1, then 1 || 0 = 1 (true).

3. Final Answer:

   1'b1 -> Option C

4. Quick Check:

   !(0) || 0 = 1 [OK]

Hint: Evaluate inner && first, then apply ! and || [OK]

Common Mistakes:

• Forgetting NOT (!) flips the value
• Evaluating OR before AND
• Confusing 1'b0 and 1'b1 values

4. Identify the error in this Verilog code snippet:

wire a, b, c;
assign c = a &| b;

medium

A. Incorrect use of &| operator

B. Missing semicolon after wire declaration

C. Using assign instead of always block

D. No error, code is correct

Solution

1. Step 1: Check operator syntax

   The operator &| does not exist in Verilog; bitwise AND is & and bitwise OR is |.

2. Step 2: Confirm correct operator usage

   To combine signals logically, use && or ||; for bitwise, use & or | separately.

3. Final Answer:

   Incorrect use of &| operator -> Option A

4. Quick Check:

   No &| operator in Verilog [OK]

Hint: Check operator symbols carefully; &| is invalid [OK]

Common Mistakes:

• Assuming &| is a valid operator
• Ignoring operator precedence
• Confusing bitwise and logical operators

5. Given inputs a, b, and c, which Verilog expression correctly implements the logic: "Output is true if either a and b are both true, or c is false"?

hard

A. assign out = (a && b) || !c;

B. assign out = !(a && b) || c;

C. assign out = (a || b) && !c;

D. assign out = !(a || b) && c;

Solution

1. Step 1: Translate the condition to logic

   Output is true if (a AND b) is true OR c is false (NOT c).

2. Step 2: Match expression with condition

   assign out = (a && b) || !c; uses (a && b) || !c which matches the condition exactly.

3. Final Answer:

   assign out = (a && b) || !c; -> Option A

4. Quick Check:

   AND + OR + NOT combined correctly [OK]

Hint: Translate words to (a && b) || !c quickly [OK]

Common Mistakes:

• Mixing OR and AND order
• Forgetting to negate c
• Using bitwise instead of logical operators