Logical operators in Verilog - Mini Project: Build & Apply

Using Logical Operators in Verilog

📖 Scenario: You are designing a simple digital circuit that decides if a system is active based on two input signals.

🎯 Goal: Build a Verilog module that uses logical operators to determine if the system should be active.

📋 What You'll Learn

Create two input signals named input_a and input_b

Create an output signal named system_active

Use logical AND and OR operators to set system_active

Print the value of system_active for given inputs

💡 Why This Matters

🌍 Real World

Logical operators are used in digital circuits to control signals based on multiple conditions, like turning devices on or off.

💼 Career

Understanding logical operators in Verilog is essential for hardware design engineers working on FPGA or ASIC development.

1

Create input signals

Create a Verilog module named system_control with two inputs called input_a and input_b of type wire.

Verilog

module system_control(input wire input_a, input wire input_b);
// Your code here
endmodule

Hint

Use module keyword and declare inputs inside parentheses.

2

Add output signal

Inside the system_control module, add an output signal called system_active of type wire.

Verilog

module system_control(input wire input_a, input wire input_b, output wire system_active);
// Your code here
endmodule

Hint

Add output wire system_active inside the module port list.

3

Use logical operators

Inside the system_control module, assign system_active to the result of input_a AND input_b OR input_a OR input_b using logical operators && and ||.

Verilog

module system_control(input wire input_a, input wire input_b, output wire system_active);
assign system_active = (input_a && input_b) || input_a || input_b;
// Your code here
endmodule

Hint

Use assign statement with logical AND && and OR || operators.

4

Test and print output

Write a testbench module named test_system_control that declares reg variables input_a and input_b, wires system_active, instantiates system_control, sets input_a = 1 and input_b = 0, and uses $display to print system_active.

Verilog

module test_system_control();
reg input_a;
reg input_b;
wire system_active;
system_control uut(input_a, input_b, system_active);
initial begin
    input_a = 1;
    input_b = 0;
    #1;
    $display("system_active = %b", system_active);
end
endmodule

Hint

Use reg for inputs, wire for output, instantiate the module, assign inputs, wait a moment, then print output.

Practice

1. Which logical operator in Verilog returns true only if both operands are true?

easy

A. ^ (XOR)

B. || (OR)

C. ! (NOT)

D. && (AND)

Solution

1. Step 1: Understand the AND operator

   The AND operator (&&) returns true only when both inputs are true.

2. Step 2: Compare with other operators

   OR (||) returns true if at least one input is true, NOT (!) inverts the input, XOR (^) returns true if inputs differ.

3. Final Answer:

   && (AND) -> Option D

4. Quick Check:

   AND needs both true = && [OK]

Hint: AND needs both true inputs to be true [OK]

Common Mistakes:

• Confusing OR (||) with AND (&&)
• Thinking NOT (!) is a binary operator
• Mixing XOR (^) with AND (&&)

2. Which of the following is the correct syntax for the logical OR operator in Verilog?

easy

A. |

B. ||

C. &

D. &&

Solution

1. Step 1: Identify logical OR syntax

   Logical OR in Verilog is represented by double vertical bars: ||.

2. Step 2: Differentiate from bitwise OR

   Single | is bitwise OR, && is logical AND, & is bitwise AND.

3. Final Answer:

   || -> Option B

4. Quick Check:

   Logical OR = || [OK]

Hint: Logical OR uses double vertical bars || [OK]

Common Mistakes:

• Using single | instead of || for logical OR
• Confusing bitwise and logical operators
• Using && instead of ||

3. What is the output of this Verilog expression if a = 1'b0 and b = 1'b1?
assign result = !(a && b) || a;

medium

A. 1'b0

B. Z (high impedance)

C. 1'b1

D. X (unknown)

Solution

1. Step 1: Evaluate inner AND (a && b)

   a = 0, b = 1, so a && b = 0 (false).

2. Step 2: Apply NOT and OR

   !(0) = 1, then 1 || 0 = 1 (true).

3. Final Answer:

   1'b1 -> Option C

4. Quick Check:

   !(0) || 0 = 1 [OK]

Hint: Evaluate inner && first, then apply ! and || [OK]

Common Mistakes:

• Forgetting NOT (!) flips the value
• Evaluating OR before AND
• Confusing 1'b0 and 1'b1 values

4. Identify the error in this Verilog code snippet:

wire a, b, c;
assign c = a &| b;

medium

A. Incorrect use of &| operator

B. Missing semicolon after wire declaration

C. Using assign instead of always block

D. No error, code is correct

Solution

1. Step 1: Check operator syntax

   The operator &| does not exist in Verilog; bitwise AND is & and bitwise OR is |.

2. Step 2: Confirm correct operator usage

   To combine signals logically, use && or ||; for bitwise, use & or | separately.

3. Final Answer:

   Incorrect use of &| operator -> Option A

4. Quick Check:

   No &| operator in Verilog [OK]

Hint: Check operator symbols carefully; &| is invalid [OK]

Common Mistakes:

• Assuming &| is a valid operator
• Ignoring operator precedence
• Confusing bitwise and logical operators

5. Given inputs a, b, and c, which Verilog expression correctly implements the logic: "Output is true if either a and b are both true, or c is false"?

hard

A. assign out = (a && b) || !c;

B. assign out = !(a && b) || c;

C. assign out = (a || b) && !c;

D. assign out = !(a || b) && c;

Solution

1. Step 1: Translate the condition to logic

   Output is true if (a AND b) is true OR c is false (NOT c).

2. Step 2: Match expression with condition

   assign out = (a && b) || !c; uses (a && b) || !c which matches the condition exactly.

3. Final Answer:

   assign out = (a && b) || !c; -> Option A

4. Quick Check:

   AND + OR + NOT combined correctly [OK]

Hint: Translate words to (a && b) || !c quickly [OK]

Common Mistakes:

• Mixing OR and AND order
• Forgetting to negate c
• Using bitwise instead of logical operators