Comparator design in Verilog - Step-by-Step Execution

Concept Flow - Comparator design

Input A, Input B

↓

Compare bits from MSB to LSB

↓

Check if A > B?

Yes→Output: A > B

No↓

Check if A < B?

Yes→Output: A < B

No↓

Output: A == B

The comparator checks two inputs bit by bit from the most significant bit to the least, deciding if one is greater, less, or equal.

Execution Sample

Verilog

module comparator(
  input [3:0] A, B,
  output reg A_gt_B, A_lt_B, A_eq_B
);
  always @(*) begin
    if (A > B) begin
      A_gt_B = 1; A_lt_B = 0; A_eq_B = 0;
    end else if (A < B) begin
      A_gt_B = 0; A_lt_B = 1; A_eq_B = 0;
    end else begin
      A_gt_B = 0; A_lt_B = 0; A_eq_B = 1;
    end
  end
endmodule

This Verilog module compares two 4-bit inputs and sets output flags for greater than, less than, or equal.

Execution Table

Step	A	B	Condition	Result	Outputs (A_gt_B, A_lt_B, A_eq_B)
1	4'b1010 (10)	4'b0101 (5)	A > B?	True	1, 0, 0
2	4'b0101 (5)	4'b1010 (10)	A > B?	False	0, 1, 0
3	4'b0111 (7)	4'b0111 (7)	A > B?	False	0, 0, 1
4	4'b0000 (0)	4'b0000 (0)	A > B?	False	0, 0, 1
5	4'b1111 (15)	4'b1110 (14)	A > B?	True	1, 0, 0
6	4'b0011 (3)	4'b0100 (4)	A > B?	False	0, 1, 0

💡 All comparisons done for given inputs, outputs set accordingly.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6
A_gt_B	x	1	0	0	0	1	0
A_lt_B	x	0	1	0	0	0	1
A_eq_B	x	0	0	1	1	0	0

Key Moments - 3 Insights

Why do we check A > B first before A < B?

Checking A > B first (see execution_table row 1) lets us quickly decide if A is greater. If false, then we check if A is less. This order avoids confusion and ensures only one output is set.

What happens if A equals B?

When A equals B (rows 3 and 4), both A > B and A < B conditions are false, so the else branch sets A_eq_B to 1, indicating equality.

Why are outputs set to 0 or 1 explicitly?

Explicitly setting outputs (see code lines in execution_sample) avoids latches and ensures outputs are always defined for every input combination.

Visual Quiz - 3 Questions

Look at the execution_table, what are the outputs when A=4'b1010 and B=4'b0101?

A A_gt_B=0, A_lt_B=0, A_eq_B=1

B A_gt_B=1, A_lt_B=0, A_eq_B=0

C A_gt_B=0, A_lt_B=1, A_eq_B=0

D A_gt_B=1, A_lt_B=1, A_eq_B=0

💡 Hint

Check execution_table row 1 for inputs A=10 and B=5.

At which step in the execution_table does the comparator output equality?

A Step 3

B Step 1

C Step 2

D Step 6

💡 Hint

Look for rows where A_eq_B output is 1 in the execution_table.

If input A changes from 4'b0011 to 4'b0100 while B is 4'b0100, how does the output change?

A From A_lt_B=1 to A_lt_B=0

B From A_eq_B=1 to A_lt_B=1

C From A_lt_B=1 to A_eq_B=1

D From A_gt_B=1 to A_lt_B=1

💡 Hint

Compare variable_tracker values for A_lt_B and A_eq_B at steps 6 and hypothetical next step.

Concept Snapshot

Comparator design in Verilog:
- Inputs: two binary numbers (e.g., 4-bit A and B)
- Compare using if-else: if (A > B), else if (A < B), else equal
- Outputs: flags for A_gt_B, A_lt_B, A_eq_B
- Always block with combinational logic
- Explicitly set all outputs to avoid latches

Full Transcript

This visual execution trace shows how a Verilog comparator works by comparing two 4-bit inputs A and B. The comparator checks if A is greater than B, less than B, or equal to B. The code uses an always block with if-else statements to set output flags accordingly. The execution table walks through different input pairs, showing the condition checked and the outputs set. The variable tracker shows how output signals change after each comparison. Key moments clarify why the order of checks matters and how equality is detected. The quiz questions test understanding of outputs for given inputs and changes. This helps beginners see step-by-step how the comparator decides the relationship between two numbers.

Practice

1.

What is the main purpose of a comparator in Verilog?

easy

A. To store data temporarily

B. To check if one number is greater, less, or equal to another

C. To add two numbers together

D. To generate clock signals

Solution

1. Step 1: Understand comparator function

   A comparator compares two values to determine their relationship.

2. Step 2: Identify correct purpose

   Only To check if one number is greater, less, or equal to another describes comparing numbers, which is the comparator's job.

3. Final Answer:

   To check if one number is greater, less, or equal to another -> Option B

4. Quick Check:

   Comparator = Compare numbers [OK]

Hint: Comparator compares values, not adds or stores [OK]

Common Mistakes:

• Confusing comparator with adder
• Thinking comparator stores data
• Mixing comparator with clock generator

2.

Which of the following is the correct way to start an always block for a comparator that reacts to changes in inputs a and b?

easy

A. always @(a, b) begin

B. always @(posedge clk) begin

C. always @(a and b) begin

D. always @(a or b) begin

Solution

1. Step 1: Understand sensitivity list syntax

   In Verilog, sensitivity list uses 'or' to list signals that trigger the block.

2. Step 2: Check options

   always @(a or b) begin uses 'or' correctly. always @(a, b) begin uses comma which is not valid in Verilog sensitivity lists.

3. Final Answer:

   always @(a or b) begin -> Option D

4. Quick Check:

   Sensitivity list uses 'or' between signals [OK]

Hint: Use 'or' between signals in sensitivity list [OK]

Common Mistakes:

• Using commas instead of 'or' in sensitivity list
• Using 'and' instead of 'or'
• Using clock edge when not needed

3.

Given the following Verilog code snippet, what will be the output signals gt, lt, and eq if a = 5 and b = 3?

module comp(input [3:0] a, b, output reg gt, lt, eq);
  always @(a or b) begin
    if (a > b) begin
      gt = 1; lt = 0; eq = 0;
    end else if (a < b) begin
      gt = 0; lt = 1; eq = 0;
    end else begin
      gt = 0; lt = 0; eq = 1;
    end
  end
endmodule

medium

A. gt=0, lt=0, eq=1

B. gt=0, lt=1, eq=0

C. gt=1, lt=0, eq=0

D. gt=1, lt=1, eq=0

Solution

1. Step 1: Compare values a=5 and b=3

   Since 5 is greater than 3, the condition 'a > b' is true.

2. Step 2: Determine output signals

   For 'a > b', gt=1, lt=0, eq=0 as per code.

3. Final Answer:

   gt=1, lt=0, eq=0 -> Option C

4. Quick Check:

   5 > 3 means gt=1 [OK]

Hint: Check which condition is true first [OK]

Common Mistakes:

• Mixing up greater than and less than
• Setting multiple outputs to 1 incorrectly
• Ignoring else conditions

4.

Identify the error in this comparator code snippet:

module comp(input [3:0] a, b, output reg gt, lt, eq);
  always @(a, b) begin
    if (a > b)
      gt = 1; lt = 0; eq = 0;
    else if (a < b)
      gt = 0; lt = 1; eq = 0;
    else
      gt = 0; lt = 0; eq = 1;
  end
endmodule

medium

A. Missing begin-end blocks after if and else if

B. Incorrect sensitivity list syntax

C. Output signals should be wires, not regs

D. Using non-blocking assignments instead of blocking

Solution

1. Step 1: Check if-else statement structure

   Multiple statements after if need to be grouped with begin-end blocks.

2. Step 2: Identify missing begin-end

   Here, multiple assignments after if and else if lack begin-end, causing syntax errors.

3. Final Answer:

   Missing begin-end blocks after if and else if -> Option A

4. Quick Check:

   Multiple statements need begin-end [OK]

Hint: Use begin-end for multiple statements in if blocks [OK]

Common Mistakes:

• Forgetting begin-end with multiple statements
• Confusing sensitivity list syntax
• Wrong data type for outputs

5.

You want to design a 4-bit comparator that sets gt high if a > b, lt high if a < b, and eq high if equal. However, you also want to ignore the comparison if either a or b is zero (all bits zero), setting all outputs low in that case. Which Verilog code snippet correctly implements this?

hard

A. always @(a or b) begin
if (a == 0 || b == 0) begin
gt = 0; lt = 0; eq = 0;
end else if (a > b) begin
gt = 1; lt = 0; eq = 0;
end else if (a < b) begin
gt = 0; lt = 1; eq = 0;
end else begin
gt = 0; lt = 0; eq = 1;
end
end

B. always @(a or b) begin
if (a == 0 && b == 0) begin
gt = 0; lt = 0; eq = 0;
end else if (a > b) begin
gt = 1; lt = 0; eq = 0;
end else if (a < b) begin
gt = 0; lt = 1; eq = 0;
end else begin
gt = 0; lt = 0; eq = 1;
end
end

C. always @(a or b) begin
if (a != 0 && b != 0) begin
if (a > b) begin
gt = 1; lt = 0; eq = 0;
end else if (a < b) begin
gt = 0; lt = 1; eq = 0;
end else begin
gt = 0; lt = 0; eq = 1;
end
end else begin
gt = 0; lt = 0; eq = 0;
end
end

D. always @(a or b) begin
if (a == 0 || b == 0) begin
gt = 1; lt = 1; eq = 1;
end else if (a > b) begin
gt = 1; lt = 0; eq = 0;
end else if (a < b) begin
gt = 0; lt = 1; eq = 0;
end else begin
gt = 0; lt = 0; eq = 1;
end
end

Solution

1. Step 1: Understand the zero check condition

   The requirement is to ignore comparison if either a or b is zero, so use 'a == 0 || b == 0'.

2. Step 2: Verify output assignments

   always @(a or b) begin if (a == 0 || b == 0) begin gt = 0; lt = 0; eq = 0; end else if (a > b) begin gt = 1; lt = 0; eq = 0; end else if (a < b) begin gt = 0; lt = 1; eq = 0; end else begin gt = 0; lt = 0; eq = 1; end end sets all outputs low when either input is zero, then compares normally otherwise.

3. Final Answer:

   Option A code snippet -> Option A

4. Quick Check:

   Use '||' to check either zero, outputs low [OK]

Hint: Use '||' to check either zero, set outputs low [OK]

Common Mistakes:

• Using '&&' instead of '||' for zero check
• Setting outputs high when inputs are zero
• Not handling zero inputs separately