Comparator design in Verilog - Mini Project: Build & Apply

Comparator Design in Verilog

📖 Scenario: You are designing a simple digital circuit that compares two 4-bit numbers. This is useful in many electronics projects, like deciding which sensor reading is higher or controlling devices based on thresholds.

🎯 Goal: Build a Verilog module called comparator that takes two 4-bit inputs a and b and outputs three signals: gt (a > b), lt (a < b), and eq (a == b).

📋 What You'll Learn

Create a Verilog module named comparator with inputs a and b (4 bits each).

Add output signals gt, lt, and eq.

Use combinational logic to compare a and b.

Print the comparison results in the testbench.

💡 Why This Matters

🌍 Real World

Comparators are used in digital circuits to make decisions, like controlling devices or sorting numbers.

💼 Career

Understanding comparator design is essential for hardware engineers and anyone working with digital logic and FPGA programming.

1

Create the comparator module with inputs and outputs

Write a Verilog module named comparator with two 4-bit inputs called a and b, and three 1-bit outputs called gt, lt, and eq. Do not add any logic yet.

Verilog

module comparator(input [3:0] a, input [3:0] b, output gt, output lt, output eq);
// Your code here
endmodule

Hint

Define the module with inputs and outputs but no logic yet.

2

Add combinational logic to compare inputs

Inside the comparator module, add continuous assignments to set gt when a is greater than b, lt when a is less than b, and eq when a equals b. Use the operators >, <, and ==.

Verilog

module comparator(input [3:0] a, input [3:0] b, output gt, output lt, output eq);
  assign gt = 0;
  assign lt = 0;
  assign eq = 0;
  // Your code here
endmodule

Hint

Use continuous assignments with comparison operators.

3

Create a testbench to test the comparator

Write a testbench module named testbench that declares a and b as 4-bit registers and gt, lt, and eq as wires. Instantiate the comparator module. Assign a = 4 and b = 7 initially.

Verilog

module comparator(input [3:0] a, input [3:0] b, output gt, output lt, output eq);
  assign gt = (a > b);
  assign lt = (a < b);
  assign eq = (a == b);
endmodule

module testbench;
  reg [3:0] a;
  reg [3:0] b;
  wire gt;
  wire lt;
  wire eq;

  // Your code here
endmodule

Hint

Instantiate the comparator and set initial values for a and b.

4

Display the comparison results

In the testbench module, inside the initial block, add a $monitor statement to print the values of a, b, gt, lt, and eq. Then add a delay of 10 time units and change a to 9 and b to 2 to see different results.

Verilog

module comparator(input [3:0] a, input [3:0] b, output gt, output lt, output eq);
  assign gt = (a > b);
  assign lt = (a < b);
  assign eq = (a == b);
endmodule

module testbench;
  reg [3:0] a;
  reg [3:0] b;
  wire gt;
  wire lt;
  wire eq;

  comparator uut(.a(a), .b(b), .gt(gt), .lt(lt), .eq(eq));

  initial begin
    a = 4;
    b = 7;
    // Your code here
  end
endmodule

Hint

Use $monitor to print values and delays to change inputs.

Practice

1.

What is the main purpose of a comparator in Verilog?

easy

A. To store data temporarily

B. To check if one number is greater, less, or equal to another

C. To add two numbers together

D. To generate clock signals

Solution

1. Step 1: Understand comparator function

   A comparator compares two values to determine their relationship.

2. Step 2: Identify correct purpose

   Only To check if one number is greater, less, or equal to another describes comparing numbers, which is the comparator's job.

3. Final Answer:

   To check if one number is greater, less, or equal to another -> Option B

4. Quick Check:

   Comparator = Compare numbers [OK]

Hint: Comparator compares values, not adds or stores [OK]

Common Mistakes:

• Confusing comparator with adder
• Thinking comparator stores data
• Mixing comparator with clock generator

2.

Which of the following is the correct way to start an always block for a comparator that reacts to changes in inputs a and b?

easy

A. always @(a, b) begin

B. always @(posedge clk) begin

C. always @(a and b) begin

D. always @(a or b) begin

Solution

1. Step 1: Understand sensitivity list syntax

   In Verilog, sensitivity list uses 'or' to list signals that trigger the block.

2. Step 2: Check options

   always @(a or b) begin uses 'or' correctly. always @(a, b) begin uses comma which is not valid in Verilog sensitivity lists.

3. Final Answer:

   always @(a or b) begin -> Option D

4. Quick Check:

   Sensitivity list uses 'or' between signals [OK]

Hint: Use 'or' between signals in sensitivity list [OK]

Common Mistakes:

• Using commas instead of 'or' in sensitivity list
• Using 'and' instead of 'or'
• Using clock edge when not needed

3.

Given the following Verilog code snippet, what will be the output signals gt, lt, and eq if a = 5 and b = 3?

module comp(input [3:0] a, b, output reg gt, lt, eq);
  always @(a or b) begin
    if (a > b) begin
      gt = 1; lt = 0; eq = 0;
    end else if (a < b) begin
      gt = 0; lt = 1; eq = 0;
    end else begin
      gt = 0; lt = 0; eq = 1;
    end
  end
endmodule

medium

A. gt=0, lt=0, eq=1

B. gt=0, lt=1, eq=0

C. gt=1, lt=0, eq=0

D. gt=1, lt=1, eq=0

Solution

1. Step 1: Compare values a=5 and b=3

   Since 5 is greater than 3, the condition 'a > b' is true.

2. Step 2: Determine output signals

   For 'a > b', gt=1, lt=0, eq=0 as per code.

3. Final Answer:

   gt=1, lt=0, eq=0 -> Option C

4. Quick Check:

   5 > 3 means gt=1 [OK]

Hint: Check which condition is true first [OK]

Common Mistakes:

• Mixing up greater than and less than
• Setting multiple outputs to 1 incorrectly
• Ignoring else conditions

4.

Identify the error in this comparator code snippet:

module comp(input [3:0] a, b, output reg gt, lt, eq);
  always @(a, b) begin
    if (a > b)
      gt = 1; lt = 0; eq = 0;
    else if (a < b)
      gt = 0; lt = 1; eq = 0;
    else
      gt = 0; lt = 0; eq = 1;
  end
endmodule

medium

A. Missing begin-end blocks after if and else if

B. Incorrect sensitivity list syntax

C. Output signals should be wires, not regs

D. Using non-blocking assignments instead of blocking

Solution

1. Step 1: Check if-else statement structure

   Multiple statements after if need to be grouped with begin-end blocks.

2. Step 2: Identify missing begin-end

   Here, multiple assignments after if and else if lack begin-end, causing syntax errors.

3. Final Answer:

   Missing begin-end blocks after if and else if -> Option A

4. Quick Check:

   Multiple statements need begin-end [OK]

Hint: Use begin-end for multiple statements in if blocks [OK]

Common Mistakes:

• Forgetting begin-end with multiple statements
• Confusing sensitivity list syntax
• Wrong data type for outputs

5.

You want to design a 4-bit comparator that sets gt high if a > b, lt high if a < b, and eq high if equal. However, you also want to ignore the comparison if either a or b is zero (all bits zero), setting all outputs low in that case. Which Verilog code snippet correctly implements this?

hard

A. always @(a or b) begin
if (a == 0 || b == 0) begin
gt = 0; lt = 0; eq = 0;
end else if (a > b) begin
gt = 1; lt = 0; eq = 0;
end else if (a < b) begin
gt = 0; lt = 1; eq = 0;
end else begin
gt = 0; lt = 0; eq = 1;
end
end

B. always @(a or b) begin
if (a == 0 && b == 0) begin
gt = 0; lt = 0; eq = 0;
end else if (a > b) begin
gt = 1; lt = 0; eq = 0;
end else if (a < b) begin
gt = 0; lt = 1; eq = 0;
end else begin
gt = 0; lt = 0; eq = 1;
end
end

C. always @(a or b) begin
if (a != 0 && b != 0) begin
if (a > b) begin
gt = 1; lt = 0; eq = 0;
end else if (a < b) begin
gt = 0; lt = 1; eq = 0;
end else begin
gt = 0; lt = 0; eq = 1;
end
end else begin
gt = 0; lt = 0; eq = 0;
end
end

D. always @(a or b) begin
if (a == 0 || b == 0) begin
gt = 1; lt = 1; eq = 1;
end else if (a > b) begin
gt = 1; lt = 0; eq = 0;
end else if (a < b) begin
gt = 0; lt = 1; eq = 0;
end else begin
gt = 0; lt = 0; eq = 1;
end
end

Solution

1. Step 1: Understand the zero check condition

   The requirement is to ignore comparison if either a or b is zero, so use 'a == 0 || b == 0'.

2. Step 2: Verify output assignments

   always @(a or b) begin if (a == 0 || b == 0) begin gt = 0; lt = 0; eq = 0; end else if (a > b) begin gt = 1; lt = 0; eq = 0; end else if (a < b) begin gt = 0; lt = 1; eq = 0; end else begin gt = 0; lt = 0; eq = 1; end end sets all outputs low when either input is zero, then compares normally otherwise.

3. Final Answer:

   Option A code snippet -> Option A

4. Quick Check:

   Use '||' to check either zero, outputs low [OK]

Hint: Use '||' to check either zero, set outputs low [OK]

Common Mistakes:

• Using '&&' instead of '||' for zero check
• Setting outputs high when inputs are zero
• Not handling zero inputs separately