Comparator design in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of 2-bit Comparator Module

What is the output of this 2-bit comparator module when inputs A=2'b10 and B=2'b01?

Verilog

module comparator_2bit(input [1:0] A, input [1:0] B, output reg A_gt_B);
  always @(*) begin
    if (A > B)
      A_gt_B = 1'b1;
    else
      A_gt_B = 1'b0;
  end
endmodule

A A_gt_B = 1'b1

B A_gt_B = 1'bx (unknown)

C A_gt_B = 1'b0

D A_gt_B = 1'bz (high impedance)

💡 Hint

Compare the binary values 2'b10 (decimal 2) and 2'b01 (decimal 1).

Since 2 is greater than 1, the output A_gt_B will be 1'b1.

❓ Predict Output

intermediate

Output of 4-bit Equality Comparator

What is the output of this 4-bit equality comparator when inputs A=4'b1010 and B=4'b1010?

Verilog

module equality_comparator_4bit(input [3:0] A, input [3:0] B, output reg equal);
  always @(*) begin
    if (A == B)
      equal = 1'b1;
    else
      equal = 1'b0;
  end
endmodule

A equal = 1'b0

B equal = 1'bz

C equal = 1'b1

D equal = 1'bx

💡 Hint

Check if both 4-bit inputs are exactly the same.

Both inputs are 4'b1010, so equal is set to 1'b1.

🔧 Debug

advanced

Identify the Error in 3-bit Comparator

What error will this 3-bit comparator code produce?

Verilog

module comparator_3bit(input [2:0] A, input [2:0] B, output reg A_lt_B);
  always @(*) begin
    if (A < B)
      A_lt_B = 1'b1;
    else
      A_lt_B = 1'b0;
  end
endmodule

A Runtime error due to uninitialized output

B SyntaxError due to missing parentheses in if condition

C No error, code runs correctly

D SyntaxError due to missing semicolon after if statement

💡 Hint

Check the syntax of the if statement in Verilog.

The if condition must be enclosed in parentheses. Missing parentheses cause a syntax error.

❓ Predict Output

advanced

Output of Signed Comparator with Negative Numbers

What is the output of this signed 4-bit comparator when A = -3 (4'b1101) and B = 2 (4'b0010)?

Verilog

module signed_comparator(input signed [3:0] A, input signed [3:0] B, output reg A_gt_B);
  always @(*) begin
    if (A > B)
      A_gt_B = 1'b1;
    else
      A_gt_B = 1'b0;
  end
endmodule

A A_gt_B = 1'b0

B A_gt_B = 1'b1

C A_gt_B = 1'bx

D A_gt_B = 1'bz

💡 Hint

Remember to interpret inputs as signed numbers.

-3 is less than 2, so A_gt_B is 1'b0.

🧠 Conceptual

expert

Number of Output Signals in a 3-way Comparator

How many output signals are needed to fully represent the comparison results of a 3-input comparator (inputs A, B, C) that indicates which input is the greatest?

A 1 output, encoding the index of the greatest input in binary

B 6 outputs, representing all pairwise comparisons

C 2 outputs, encoding the greatest input using a 2-bit binary code

D 3 outputs, one for each input indicating if it is the greatest

💡 Hint

Think about how to show which input is the greatest clearly and simply.

Each output corresponds to one input and is high if that input is the greatest. This requires 3 outputs.

Practice

1.

What is the main purpose of a comparator in Verilog?

easy

A. To store data temporarily

B. To check if one number is greater, less, or equal to another

C. To add two numbers together

D. To generate clock signals

Solution

1. Step 1: Understand comparator function

   A comparator compares two values to determine their relationship.

2. Step 2: Identify correct purpose

   Only To check if one number is greater, less, or equal to another describes comparing numbers, which is the comparator's job.

3. Final Answer:

   To check if one number is greater, less, or equal to another -> Option B

4. Quick Check:

   Comparator = Compare numbers [OK]

Hint: Comparator compares values, not adds or stores [OK]

Common Mistakes:

• Confusing comparator with adder
• Thinking comparator stores data
• Mixing comparator with clock generator

2.

Which of the following is the correct way to start an always block for a comparator that reacts to changes in inputs a and b?

easy

A. always @(a, b) begin

B. always @(posedge clk) begin

C. always @(a and b) begin

D. always @(a or b) begin

Solution

1. Step 1: Understand sensitivity list syntax

   In Verilog, sensitivity list uses 'or' to list signals that trigger the block.

2. Step 2: Check options

   always @(a or b) begin uses 'or' correctly. always @(a, b) begin uses comma which is not valid in Verilog sensitivity lists.

3. Final Answer:

   always @(a or b) begin -> Option D

4. Quick Check:

   Sensitivity list uses 'or' between signals [OK]

Hint: Use 'or' between signals in sensitivity list [OK]

Common Mistakes:

• Using commas instead of 'or' in sensitivity list
• Using 'and' instead of 'or'
• Using clock edge when not needed

3.

Given the following Verilog code snippet, what will be the output signals gt, lt, and eq if a = 5 and b = 3?

module comp(input [3:0] a, b, output reg gt, lt, eq);
  always @(a or b) begin
    if (a > b) begin
      gt = 1; lt = 0; eq = 0;
    end else if (a < b) begin
      gt = 0; lt = 1; eq = 0;
    end else begin
      gt = 0; lt = 0; eq = 1;
    end
  end
endmodule

medium

A. gt=0, lt=0, eq=1

B. gt=0, lt=1, eq=0

C. gt=1, lt=0, eq=0

D. gt=1, lt=1, eq=0

Solution

1. Step 1: Compare values a=5 and b=3

   Since 5 is greater than 3, the condition 'a > b' is true.

2. Step 2: Determine output signals

   For 'a > b', gt=1, lt=0, eq=0 as per code.

3. Final Answer:

   gt=1, lt=0, eq=0 -> Option C

4. Quick Check:

   5 > 3 means gt=1 [OK]

Hint: Check which condition is true first [OK]

Common Mistakes:

• Mixing up greater than and less than
• Setting multiple outputs to 1 incorrectly
• Ignoring else conditions

4.

Identify the error in this comparator code snippet:

module comp(input [3:0] a, b, output reg gt, lt, eq);
  always @(a, b) begin
    if (a > b)
      gt = 1; lt = 0; eq = 0;
    else if (a < b)
      gt = 0; lt = 1; eq = 0;
    else
      gt = 0; lt = 0; eq = 1;
  end
endmodule

medium

A. Missing begin-end blocks after if and else if

B. Incorrect sensitivity list syntax

C. Output signals should be wires, not regs

D. Using non-blocking assignments instead of blocking

Solution

1. Step 1: Check if-else statement structure

   Multiple statements after if need to be grouped with begin-end blocks.

2. Step 2: Identify missing begin-end

   Here, multiple assignments after if and else if lack begin-end, causing syntax errors.

3. Final Answer:

   Missing begin-end blocks after if and else if -> Option A

4. Quick Check:

   Multiple statements need begin-end [OK]

Hint: Use begin-end for multiple statements in if blocks [OK]

Common Mistakes:

• Forgetting begin-end with multiple statements
• Confusing sensitivity list syntax
• Wrong data type for outputs

5.

You want to design a 4-bit comparator that sets gt high if a > b, lt high if a < b, and eq high if equal. However, you also want to ignore the comparison if either a or b is zero (all bits zero), setting all outputs low in that case. Which Verilog code snippet correctly implements this?

hard

A. always @(a or b) begin
if (a == 0 || b == 0) begin
gt = 0; lt = 0; eq = 0;
end else if (a > b) begin
gt = 1; lt = 0; eq = 0;
end else if (a < b) begin
gt = 0; lt = 1; eq = 0;
end else begin
gt = 0; lt = 0; eq = 1;
end
end

B. always @(a or b) begin
if (a == 0 && b == 0) begin
gt = 0; lt = 0; eq = 0;
end else if (a > b) begin
gt = 1; lt = 0; eq = 0;
end else if (a < b) begin
gt = 0; lt = 1; eq = 0;
end else begin
gt = 0; lt = 0; eq = 1;
end
end

C. always @(a or b) begin
if (a != 0 && b != 0) begin
if (a > b) begin
gt = 1; lt = 0; eq = 0;
end else if (a < b) begin
gt = 0; lt = 1; eq = 0;
end else begin
gt = 0; lt = 0; eq = 1;
end
end else begin
gt = 0; lt = 0; eq = 0;
end
end

D. always @(a or b) begin
if (a == 0 || b == 0) begin
gt = 1; lt = 1; eq = 1;
end else if (a > b) begin
gt = 1; lt = 0; eq = 0;
end else if (a < b) begin
gt = 0; lt = 1; eq = 0;
end else begin
gt = 0; lt = 0; eq = 1;
end
end

Solution

1. Step 1: Understand the zero check condition

   The requirement is to ignore comparison if either a or b is zero, so use 'a == 0 || b == 0'.

2. Step 2: Verify output assignments

   always @(a or b) begin if (a == 0 || b == 0) begin gt = 0; lt = 0; eq = 0; end else if (a > b) begin gt = 1; lt = 0; eq = 0; end else if (a < b) begin gt = 0; lt = 1; eq = 0; end else begin gt = 0; lt = 0; eq = 1; end end sets all outputs low when either input is zero, then compares normally otherwise.

3. Final Answer:

   Option A code snippet -> Option A

4. Quick Check:

   Use '||' to check either zero, outputs low [OK]

Hint: Use '||' to check either zero, set outputs low [OK]

Common Mistakes:

• Using '&&' instead of '||' for zero check
• Setting outputs high when inputs are zero
• Not handling zero inputs separately