UART receiver module in Verilog - Step-by-Step Execution

Concept Flow - UART receiver module

Idle: Wait for Start Bit

↓

Detect Start Bit (rx line goes LOW)

↓

Start Bit Confirmed

↓

Sample Data Bits (8 bits)

↓

Sample Stop Bit

↓

Set Data Ready Flag

↓

Return to Idle

The UART receiver waits for a start bit, then samples 8 data bits, followed by a stop bit, and finally signals data is ready.

Execution Sample

Verilog

module uart_rx(
  input clk, input rst, input rx,
  output reg [7:0] data, output reg data_ready
);

This code snippet defines the UART receiver module inputs and outputs.

Execution Table

Step	rx line	State	Bit Counter	Sampled Bit	Data Register	data_ready
1	1 (idle)	Idle	0	-	00000000	0
2	0 (start bit)	Start Bit Detect	0	-	00000000	0
3	0 (start bit)	Start Bit Confirmed	0	-	00000000	0
4	1 (bit0)	Receiving Data	1	1	00000001	0
5	0 (bit1)	Receiving Data	2	0	00000001	0
6	1 (bit2)	Receiving Data	3	1	00000101	0
7	0 (bit3)	Receiving Data	4	0	00000101	0
8	1 (bit4)	Receiving Data	5	1	00010101	0
9	1 (bit5)	Receiving Data	6	1	00110101	0
10	0 (bit6)	Receiving Data	7	0	00110101	0
11	1 (bit7)	Receiving Data	8	1	10110101	0
12	1 (stop bit)	Stop Bit Check	8	-	10110101	0
13	1 (idle)	Data Ready	8	-	10110101	1
14	1 (idle)	Idle	0	-	10110101	0

💡 After stop bit received and data_ready set, module returns to Idle state.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7	After 8	After 9	After 10	After 11	After 12	After 13	Final
State	Idle	Start Bit Detect	Start Bit Confirmed	Receiving Data	Receiving Data	Receiving Data	Receiving Data	Receiving Data	Receiving Data	Receiving Data	Receiving Data	Stop Bit Check	Data Ready	Idle	Idle
Bit Counter	0	0	0	1	2	3	4	5	6	7	8	8	8	0	0
Data Register	00000000	00000000	00000000	00000001	00000001	00000101	00000101	00010101	00110101	00110101	10110101	10110101	10110101	10110101	10110101
data_ready	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0

Key Moments - 3 Insights

Why does the receiver wait for the rx line to go LOW before starting to read data?

The rx line going LOW signals the start bit, which tells the receiver that data transmission is beginning (see execution_table step 2). Without detecting this, the receiver won't know when to start sampling bits.

Why is the bit counter incremented only during the Receiving Data state?

Because the bit counter tracks how many data bits have been read. It starts counting after the start bit is confirmed (execution_table steps 4-11) and stops after 8 bits are received.

When and why is data_ready set to 1?

data_ready is set after the stop bit is received and verified (step 13). This signals that a full byte has been received and is ready to be read.

Visual Quiz - 3 Questions

Look at the execution_table at step 6. What is the value of the Data Register?

A 00000001

B 00000101

C 00010101

D 00110101

💡 Hint

Check the 'Data Register' column at step 6 in the execution_table.

At which step does the data_ready flag become 1?

A Step 13

B Step 11

C Step 12

D Step 14

💡 Hint

Look at the 'data_ready' column in the execution_table and find where it changes to 1.

If the rx line never goes LOW, what state does the receiver stay in according to the execution_table?

A Start Bit Detect

B Receiving Data

C Idle

D Data Ready

💡 Hint

See the 'State' column at step 1 where rx line is 1 (idle).

Concept Snapshot

UART Receiver Module:
- Waits for rx line LOW (start bit)
- Samples 8 data bits sequentially
- Checks stop bit (rx line HIGH)
- Sets data_ready flag when byte received
- Returns to idle to wait for next byte

Full Transcript

This UART receiver module waits in an idle state until it detects the rx line going LOW, which signals the start bit. Once detected, it confirms the start bit and begins sampling 8 data bits one by one, storing them in a data register. After all data bits are received, it samples the stop bit to ensure proper transmission. When the stop bit is valid, it sets the data_ready flag to indicate a full byte is available. Then it returns to idle to wait for the next start bit. The bit counter tracks how many data bits have been read. The data register accumulates bits as they are sampled. This process repeats for every byte received over UART.

Practice

1. What is the primary role of a UART receiver module in digital communication?

easy

A. To read serial bits and convert them into bytes

B. To generate clock signals for data transmission

C. To encode parallel data into serial format

D. To amplify the input signal strength

Solution

1. Step 1: Understand UART receiver function

   A UART receiver reads incoming serial bits one by one.

2. Step 2: Conversion to bytes

   It collects these bits and converts them into a byte for further processing.

3. Final Answer:

   To read serial bits and convert them into bytes -> Option A

4. Quick Check:

   UART receiver = serial bits to bytes [OK]

Hint: Remember UART receiver converts serial bits to bytes [OK]

Common Mistakes:

• Confusing receiver with transmitter
• Thinking it generates clock signals
• Assuming it amplifies signals

2. Which of the following is the correct Verilog syntax to declare a 8-bit output register named data_out in a UART receiver module?

easy

A. output reg [7:0] data_out;

B. reg output [7:0] data_out;

C. output [7:0] reg data_out;

D. reg [7:0] output data_out;

Solution

1. Step 1: Identify correct order for output register declaration

   In Verilog, the correct order is 'output reg [width] name;'.

2. Step 2: Check each option

   Only output reg [7:0] data_out; follows this syntax correctly.

3. Final Answer:

   output reg [7:0] data_out; -> Option A

4. Quick Check:

   output reg declaration syntax = output reg [7:0] data_out; [OK]

Hint: Use 'output reg [width] name;' for output registers [OK]

Common Mistakes:

• Placing 'reg' after 'output'
• Swapping 'output' and 'reg' keywords
• Omitting bit width

3. Given the following Verilog snippet inside a UART receiver module:

always @(posedge clk) begin
  if (start_bit_detected) begin
    bit_count <= 0;
    data_reg <= 0;
  end else if (bit_sample_enable) begin
    data_reg <= {serial_in, data_reg[7:1]};
    bit_count <= bit_count + 1;
  end
end

What will be the value of data_reg after 3 samples if serial_in was 1, 0, then 1 in consecutive samples?

medium

A. 00000101 (binary)

B. 10100000 (binary)

C. 00000011 (binary)

D. 11100000 (binary)

Solution

1. Step 1: Understand bit shifting in data_reg

   Each sample shifts data_reg right by 1 and inserts serial_in at MSB.

2. Step 2: Calculate data_reg after each sample

   Initial data_reg=00000000
   Sample 1 (serial_in=1): data_reg=10000000
   Sample 2 (serial_in=0): data_reg=01000000
   Sample 3 (serial_in=1): data_reg=10100000
   Thus, after 3 samples, data_reg = 10100000 (binary)

3. Final Answer:

   10100000 (binary) -> Option B

4. Quick Check:

   Shift right + insert serial_in MSB = 10100000 [OK]

Hint: Track bit shifts and insertions stepwise [OK]

Common Mistakes:

• Confusing MSB and LSB positions
• Assuming left shift instead of right
• Ignoring initial zero value

4. In a UART receiver module, the following code snippet causes the received data to be incorrect:

always @(posedge clk) begin
  if (start_bit_detected) begin
    bit_count <= 0;
    data_reg <= 0;
  end else if (bit_sample_enable) begin
    data_reg <= {data_reg[6:0], serial_in};
    bit_count <= bit_count + 1;
  end
end

What is the likely error in this code?

medium

A. bit_count is not incremented correctly

B. The start bit is not being detected properly

C. Bits are shifted left instead of right, causing wrong bit order

D. serial_in is not sampled at the correct clock edge

Solution

1. Step 1: Analyze bit shifting direction

   The code shifts data_reg left by 1 bit and inserts serial_in at LSB.

2. Step 2: Understand UART bit order

   UART typically receives LSB first, so bits should be shifted right with serial_in at MSB to maintain correct order.

3. Final Answer:

   Bits are shifted left instead of right, causing wrong bit order -> Option C

4. Quick Check:

   Incorrect shift direction = Bits are shifted left instead of right, causing wrong bit order [OK]

Hint: UART bits usually shift right; check shift direction [OK]

Common Mistakes:

• Mixing up left and right shifts
• Ignoring bit order in UART protocol
• Assuming start bit detection error

5. You want to design a UART receiver module that sets a data_ready flag only after receiving all 8 data bits and the stop bit. Which approach correctly implements this behavior?

hard

A. Set data_ready when bit_count == 8 (only data bits)

B. Set data_ready immediately after detecting the start bit

C. Set data_ready after receiving 7 data bits only

D. Set data_ready when bit_count == 9 (8 data bits + 1 stop bit)

Solution

1. Step 1: Understand UART frame structure

   A UART frame has 1 start bit, 8 data bits, and 1 stop bit.

2. Step 2: Determine when data is fully received

   Data is ready only after all 8 data bits and the stop bit are received, so bit_count should reach 9.

3. Final Answer:

   Set data_ready when bit_count == 9 (8 data bits + 1 stop bit) -> Option D

4. Quick Check:

   Data ready after 9 bits = Set data_ready when bit_count == 9 (8 data bits + 1 stop bit) [OK]

Hint: Wait for all bits including stop bit before setting data_ready [OK]

Common Mistakes:

• Setting data_ready too early
• Ignoring stop bit in count
• Confusing start bit with data bits