UART receiver module in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

UART Receiver: Output Data Value

Given the UART receiver module below, what is the value of data_out after receiving the byte 8'b10110011?

Verilog

module uart_rx(
  input wire clk,
  input wire rst,
  input wire rx,
  output reg [7:0] data_out,
  output reg data_ready
);
  // Simplified UART receiver logic
  reg [3:0] bit_cnt = 0;
  reg [7:0] shift_reg = 0;
  reg receiving = 0;

  always @(posedge clk or posedge rst) begin
    if (rst) begin
      bit_cnt <= 0;
      shift_reg <= 0;
      data_out <= 0;
      data_ready <= 0;
      receiving <= 0;
    end else begin
      if (!receiving && rx == 0) begin // start bit detected
        receiving <= 1;
        bit_cnt <= 0;
        data_ready <= 0;
      end else if (receiving) begin
        if (bit_cnt < 8) begin
          shift_reg[bit_cnt] <= rx;
          bit_cnt <= bit_cnt + 1;
        end else begin
          data_out <= shift_reg;
          data_ready <= 1;
          receiving <= 0;
        end
      end
    end
  end
endmodule

A 8'b01001101

B 8'b11001101

C 8'b10110011

D 8'b10110110

💡 Hint

Remember UART sends LSB first, so bits are shifted in order starting from bit 0.

The UART receiver shifts in bits starting from the least significant bit (bit 0). The input byte 8'b10110011 is received bit by bit in order, so the shift register ends up holding the same value 8'b10110011.

🧠 Conceptual

intermediate

UART Receiver Start Bit Detection

In a UART receiver module, why is the start bit detected by checking if the rx line is low (0) when the receiver is idle?

A Because UART idle state is high (1), so a low signal indicates the start bit.

B Because UART idle state is low (0), so a low signal means data is being sent.

C Because the start bit is always high (1) to signal the beginning of data.

D Because the receiver ignores the start bit and waits for the stop bit.

💡 Hint

Think about the default voltage level on the UART line when no data is sent.

UART lines stay at logic high (1) when idle. The start bit is a low (0) signal that tells the receiver data is coming. Detecting a low on the line when idle means the start bit has arrived.

🔧 Debug

advanced

Identify the Bug in UART Receiver Bit Counting

What error will occur in the following UART receiver snippet when receiving 8 bits, and why?

Verilog

always @(posedge clk or posedge rst) begin
  if (rst) begin
    bit_cnt <= 0;
  end else if (receiving) begin
    if (bit_cnt <= 8) begin
      bit_cnt <= bit_cnt + 1;
    end else begin
      receiving <= 0;
    end
  end
end

A receiving will never be set to 0, causing an infinite receiving state.

B bit_cnt will count to 9 causing an off-by-one error and incorrect data reception.

C The code will cause a syntax error due to missing semicolons.

D bit_cnt will never increment because the condition is always false.

💡 Hint

Check the condition that controls bit_cnt increment and when receiving stops.

The condition 'bit_cnt <= 8' allows bit_cnt to reach 9, which is one more than the 8 bits expected. This off-by-one error causes the receiver to shift in an extra bit, corrupting data.

📝 Syntax

advanced

Syntax Error in UART Receiver Always Block

Which option contains a syntax error in the always block of a UART receiver module?

Verilog

always @(posedge clk or posedge rst) begin
  if (rst) begin
    bit_cnt <= 0
  end else begin
    bit_cnt <= bit_cnt + 1;
  end
end

A Missing semicolon after 'bit_cnt <= 0' causes syntax error.

B Using '<=' instead of '=' in always block causes syntax error.

C Missing 'begin' after 'else' causes syntax error.

D Using 'posedge' in sensitivity list is invalid syntax.

💡 Hint

Check each line for missing punctuation.

In Verilog, each statement inside begin-end must end with a semicolon. The line 'bit_cnt <= 0' is missing a semicolon, causing a syntax error.

🚀 Application

expert

UART Receiver: Number of Data Bits Received

In a UART receiver module configured for 8 data bits, no parity, and 1 stop bit, how many bits in total does the receiver process per frame including start and stop bits?

A 9 bits

B 11 bits

C 8 bits

D 10 bits

💡 Hint

Count start bit + data bits + stop bit(s).

A UART frame includes 1 start bit, 8 data bits, and 1 stop bit, totaling 10 bits per frame.

Practice

1. What is the primary role of a UART receiver module in digital communication?

easy

A. To read serial bits and convert them into bytes

B. To generate clock signals for data transmission

C. To encode parallel data into serial format

D. To amplify the input signal strength

Solution

1. Step 1: Understand UART receiver function

   A UART receiver reads incoming serial bits one by one.

2. Step 2: Conversion to bytes

   It collects these bits and converts them into a byte for further processing.

3. Final Answer:

   To read serial bits and convert them into bytes -> Option A

4. Quick Check:

   UART receiver = serial bits to bytes [OK]

Hint: Remember UART receiver converts serial bits to bytes [OK]

Common Mistakes:

• Confusing receiver with transmitter
• Thinking it generates clock signals
• Assuming it amplifies signals

2. Which of the following is the correct Verilog syntax to declare a 8-bit output register named data_out in a UART receiver module?

easy

A. output reg [7:0] data_out;

B. reg output [7:0] data_out;

C. output [7:0] reg data_out;

D. reg [7:0] output data_out;

Solution

1. Step 1: Identify correct order for output register declaration

   In Verilog, the correct order is 'output reg [width] name;'.

2. Step 2: Check each option

   Only output reg [7:0] data_out; follows this syntax correctly.

3. Final Answer:

   output reg [7:0] data_out; -> Option A

4. Quick Check:

   output reg declaration syntax = output reg [7:0] data_out; [OK]

Hint: Use 'output reg [width] name;' for output registers [OK]

Common Mistakes:

• Placing 'reg' after 'output'
• Swapping 'output' and 'reg' keywords
• Omitting bit width

3. Given the following Verilog snippet inside a UART receiver module:

always @(posedge clk) begin
  if (start_bit_detected) begin
    bit_count <= 0;
    data_reg <= 0;
  end else if (bit_sample_enable) begin
    data_reg <= {serial_in, data_reg[7:1]};
    bit_count <= bit_count + 1;
  end
end

What will be the value of data_reg after 3 samples if serial_in was 1, 0, then 1 in consecutive samples?

medium

A. 00000101 (binary)

B. 10100000 (binary)

C. 00000011 (binary)

D. 11100000 (binary)

Solution

1. Step 1: Understand bit shifting in data_reg

   Each sample shifts data_reg right by 1 and inserts serial_in at MSB.

2. Step 2: Calculate data_reg after each sample

   Initial data_reg=00000000
   Sample 1 (serial_in=1): data_reg=10000000
   Sample 2 (serial_in=0): data_reg=01000000
   Sample 3 (serial_in=1): data_reg=10100000
   Thus, after 3 samples, data_reg = 10100000 (binary)

3. Final Answer:

   10100000 (binary) -> Option B

4. Quick Check:

   Shift right + insert serial_in MSB = 10100000 [OK]

Hint: Track bit shifts and insertions stepwise [OK]

Common Mistakes:

• Confusing MSB and LSB positions
• Assuming left shift instead of right
• Ignoring initial zero value

4. In a UART receiver module, the following code snippet causes the received data to be incorrect:

always @(posedge clk) begin
  if (start_bit_detected) begin
    bit_count <= 0;
    data_reg <= 0;
  end else if (bit_sample_enable) begin
    data_reg <= {data_reg[6:0], serial_in};
    bit_count <= bit_count + 1;
  end
end

What is the likely error in this code?

medium

A. bit_count is not incremented correctly

B. The start bit is not being detected properly

C. Bits are shifted left instead of right, causing wrong bit order

D. serial_in is not sampled at the correct clock edge

Solution

1. Step 1: Analyze bit shifting direction

   The code shifts data_reg left by 1 bit and inserts serial_in at LSB.

2. Step 2: Understand UART bit order

   UART typically receives LSB first, so bits should be shifted right with serial_in at MSB to maintain correct order.

3. Final Answer:

   Bits are shifted left instead of right, causing wrong bit order -> Option C

4. Quick Check:

   Incorrect shift direction = Bits are shifted left instead of right, causing wrong bit order [OK]

Hint: UART bits usually shift right; check shift direction [OK]

Common Mistakes:

• Mixing up left and right shifts
• Ignoring bit order in UART protocol
• Assuming start bit detection error

5. You want to design a UART receiver module that sets a data_ready flag only after receiving all 8 data bits and the stop bit. Which approach correctly implements this behavior?

hard

A. Set data_ready when bit_count == 8 (only data bits)

B. Set data_ready immediately after detecting the start bit

C. Set data_ready after receiving 7 data bits only

D. Set data_ready when bit_count == 9 (8 data bits + 1 stop bit)

Solution

1. Step 1: Understand UART frame structure

   A UART frame has 1 start bit, 8 data bits, and 1 stop bit.

2. Step 2: Determine when data is fully received

   Data is ready only after all 8 data bits and the stop bit are received, so bit_count should reach 9.

3. Final Answer:

   Set data_ready when bit_count == 9 (8 data bits + 1 stop bit) -> Option D

4. Quick Check:

   Data ready after 9 bits = Set data_ready when bit_count == 9 (8 data bits + 1 stop bit) [OK]

Hint: Wait for all bits including stop bit before setting data_ready [OK]

Common Mistakes:

• Setting data_ready too early
• Ignoring stop bit in count
• Confusing start bit with data bits