Setup time and hold time concept in Verilog - Step-by-Step Execution

Concept Flow - Setup time and hold time concept

Input Data Changes

↓

Setup Time Window

↓

Clock Edge Arrival

↓

Hold Time Window

↓

Data Captured Correctly?

No→Timing Violation

Yes↓

Stable Output

Data must be stable before the clock edge (setup time) and remain stable after it (hold time) to capture correctly.

Execution Sample

Verilog

always @(posedge clk) begin
  q <= d;
end

On each rising clock edge, the data 'd' is captured into 'q' if timing constraints are met.

Execution Table

Step	Time (ns)	Data 'd' Value	Clock Edge	Setup Time Met?	Hold Time Met?	Result
1	9.5	0	No	N/A	N/A	Waiting for clock
2	10.0	0	Yes	Data stable since 9.0 (setup=1ns)	Data stable after 10.0 (hold=1ns)	Captured 0 correctly
3	10.5	1	No	N/A	N/A	Data changed after clock edge
4	11.0	1	Yes	Data stable since 10.0 (setup=1ns)	Data stable after 11.0 (hold=1ns)	Captured 1 correctly
5	11.5	0	No	N/A	N/A	Data changed after clock edge
6	12.0	0	Yes	Data stable since 11.5 (setup=0.5ns < 1ns)	Data stable after 12.0 (hold=1ns)	Setup time violated, incorrect capture
7	12.5	0	No	N/A	N/A	Data stable
8	13.0	0	Yes	Data stable since 12.5 (setup=0.5ns < 1ns)	Data stable after 13.0 (hold=1ns)	Setup time violated again
9	13.5	1	No	N/A	N/A	Data changed after clock edge
10	14.0	1	Yes	Data stable since 13.0 (setup=1ns)	Data stable after 14.0 (hold=1ns)	Captured 1 correctly

💡 Simulation ends after 5 clock edges; captures depend on setup and hold timing.

Variable Tracker

Variable	Start	After Step 2	After Step 4	After Step 6	After Step 8	After Step 10
d	0	0	1	0	0	1
clk	0	1 (posedge)	1 (posedge)	1 (posedge)	1 (posedge)	1 (posedge)
q	X (unknown)	0	1	Incorrect (due to violation)	Incorrect (due to violation)	1

Key Moments - 2 Insights

Why does the capture fail at step 6 even though the clock edge occurs?

At step 6, the data 'd' changed only 0.5ns before the clock edge, which is less than the required 1ns setup time, causing a timing violation as shown in the execution_table row 6.

What happens if data changes immediately after the clock edge?

If data changes right after the clock edge but hold time is met (data stable for 1ns after clock), the capture is still correct. This is shown at step 4 where hold time is satisfied.

Visual Quiz - 3 Questions

Look at the execution_table at step 4. What is the value of 'q' after the clock edge?

A 0

B 1

C X (unknown)

D Setup violation

💡 Hint

Refer to row 4 where data 'd' is 1 and both setup and hold times are met.

At which step does the setup time violation first occur?

A Step 6

B Step 2

C Step 10

D Step 4

💡 Hint

Check the 'Setup Time Met?' column in the execution_table for the first 'No' after a clock edge.

If the hold time was reduced to 0.5ns, which step's result would change?

A Step 6

B Step 4

C Step 8

D Step 10

💡 Hint

Look at step 8 where setup time is violated but hold time is currently met; reducing hold time affects hold time checks.

Concept Snapshot

Setup time: Data must be stable before clock edge for a minimum time.
Hold time: Data must remain stable after clock edge for a minimum time.
Violating these causes incorrect data capture.
In Verilog, data is captured on clock edges if timing is met.
Timing violations cause unpredictable outputs.

Full Transcript

Setup time and hold time are critical timing constraints in digital circuits. Setup time means data must be stable before the clock edge by a certain minimum time. Hold time means data must remain stable after the clock edge for a minimum time. In the Verilog example, data 'd' is captured into 'q' on the rising edge of 'clk'. The execution table shows data values, clock edges, and whether setup and hold times are met at each step. When setup or hold time is violated, the data capture can be incorrect, leading to timing violations. The variable tracker shows how 'd', 'clk', and 'q' change over time. Key moments clarify why timing violations cause errors and how data changes after clock edges affect capture. The visual quiz tests understanding of timing violations and their effects on data capture. This concept is essential for designing reliable digital circuits.

Practice

1. What does setup time mean in the context of flip-flops in Verilog?

easy

A. Clock must be stable before data changes.

B. Data must change exactly at the clock edge.

C. Data must be stable after the clock edge.

D. Data must be stable before the clock edge.

Solution

1. Step 1: Understand setup time definition

   Setup time is the minimum time data must be stable before the clock edge to be correctly captured.

2. Step 2: Compare options with definition

   Data must be stable before the clock edge. matches the definition exactly; others describe hold time or incorrect concepts.

3. Final Answer:

   Data must be stable before the clock edge. -> Option D

4. Quick Check:

   Setup time = data stable before clock edge [OK]

Hint: Setup time means data stable before clock edge [OK]

Common Mistakes:

• Confusing setup time with hold time
• Thinking data changes exactly at clock edge
• Mixing clock stability with data stability

2. Which of the following is the correct Verilog sensitivity list to check setup and hold timing on a positive clock edge?

easy

A. always @(clk)

B. always @(posedge clk or negedge rst)

C. always @(negedge clk or posedge rst)

D. always @(posedge data)

Solution

1. Step 1: Identify clock edge for timing checks

   Setup and hold times relate to the clock edge, usually positive edge for flip-flops.

2. Step 2: Match sensitivity list syntax

   always @(posedge clk or negedge rst) uses posedge clk which is correct; others use wrong edges or signals.

3. Final Answer:

   always @(posedge clk or negedge rst) -> Option B

4. Quick Check:

   Use posedge clk for setup/hold timing [OK]

Hint: Use posedge clk in sensitivity list for timing checks [OK]

Common Mistakes:

• Using negedge clk instead of posedge
• Including data in sensitivity list incorrectly
• Missing reset signal in sensitivity list

3. Consider this Verilog snippet for a flip-flop:

always @(posedge clk) begin
  q <= d;
end

If the data d changes 2 ns after the clock edge and hold time is 3 ns, what happens?

medium

A. Data is not captured correctly because hold time is violated.

B. Data is captured correctly because setup time is met.

C. Data is captured correctly because hold time is met.

D. Data is not captured correctly because setup time is violated.

Solution

1. Step 1: Analyze timing given

   Data changes 2 ns after clock edge; hold time required is 3 ns.

2. Step 2: Check hold time condition

   Hold time means data must remain stable after clock edge for 3 ns. Data changes 2 ns after clock edge, which is less than 3 ns, so hold time is violated.

3. Final Answer:

   Data is not captured correctly because hold time is violated. -> Option A

4. Quick Check:

   Hold time violated = data unstable after clock edge [OK]

Hint: Hold time means data stable after clock edge [OK]

Common Mistakes:

• Confusing setup and hold time directions
• Assuming data change 2 ns after meets 3 ns hold time
• Ignoring hold time violation impact

4. Identify the error in this Verilog code related to setup and hold time:

always @(posedge clk) begin
  q <= d;
end

initial begin
  d = 1'b0;
  #1 d = 1'b1; // Data changes 1 ns after clock edge
end

medium

A. Data changes violate setup time before clock edge.

B. No error; code is correct.

C. Data changes violate hold time after clock edge.

D. Clock edge is not defined correctly.

Solution

1. Step 1: Understand timing of data change

   Data d changes 1 ns after clock edge, violating hold time which requires data stable after clock edge.

2. Step 2: Identify violation type

   Hold time violation occurs because data must remain stable for some time after clock edge; changing data 1 ns after clock edge breaks this.

3. Final Answer:

   Data changes violate hold time after clock edge. -> Option C

4. Quick Check:

   Hold time violation = data changes too soon after clock [OK]

Hint: Data must stay stable after clock edge to avoid hold violation [OK]

Common Mistakes:

• Thinking data change after clock edge affects setup time
• Ignoring timing of data relative to clock
• Assuming no timing constraints in initial block

5. You have a flip-flop with setup time 4 ns and hold time 2 ns. The clock period is 10 ns. If data changes 3 ns before clock edge and 1 ns after clock edge, what is the best way to fix timing violations in Verilog?

hard

A. Delay data change to at least 4 ns before clock edge and hold it stable 2 ns after clock edge.

B. Change clock period to 6 ns to fit data changes.

C. Remove the flip-flop and use combinational logic.

D. Ignore timing; synthesis tools will fix automatically.

Solution

1. Step 1: Analyze timing requirements

   Setup time requires data stable 4 ns before clock edge; hold time requires data stable 2 ns after clock edge.

2. Step 2: Compare with current data changes

   Data changes 3 ns before clock edge (violates setup) and 1 ns after clock edge (violates hold).

3. Step 3: Fix timing by adjusting data timing

   Delay data change to meet setup (≥4 ns before) and hold (≥2 ns after) times to avoid violations.

4. Final Answer:

   Delay data change to at least 4 ns before clock edge and hold it stable 2 ns after clock edge. -> Option A

5. Quick Check:

   Meet setup and hold timing by adjusting data timing [OK]

Hint: Adjust data timing to meet setup and hold times [OK]

Common Mistakes:

• Reducing clock period causing more violations
• Removing flip-flop ignoring timing needs
• Relying on tools without fixing timing