Setup time and hold time concept in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Setup time violation detection in flip-flop timing

Consider a D flip-flop with a clock period of 10ns, setup time of 2ns, and data arrival at 9ns after the clock edge. What will be the output Q after the clock edge?

Verilog

module test;
  reg clk, d;
  wire q;
  reg [3:0] time;

  initial begin
    clk = 0;
    d = 0;
    time = 0;
    forever #5 clk = ~clk; // 10ns clock period
  end

  always @(posedge clk) begin
    $display($time, ": Clock edge detected, Q = %b", q);
  end

  always @(time) begin
    if (time == 9) d = 1; // data changes at 9ns
  end

  always #1 time = time + 1;

  dff my_dff(.clk(clk), .d(d), .q(q));

  initial #30 $finish;
endmodule

module dff(input clk, input d, output reg q);
  always @(posedge clk) begin
    q <= d;
  end
endmodule

A Q toggles unpredictably due to hold time violation

B Simulation will produce a syntax error due to missing semicolon

C Q updates to 1 correctly because data arrived before clock edge

D Q remains 0 because data arrived too late violating setup time

💡 Hint

Setup time means data must be stable before the clock edge by a certain time.

Since data changes at 9ns and clock edge is at 10ns, data is only stable 1ns before clock edge, less than the 2ns setup time. This causes a setup time violation, so Q does not update to new data.

❓ Predict Output

intermediate

Hold time violation effect on flip-flop output

A D flip-flop has a hold time of 1ns. If data changes exactly at the clock edge, what is the expected behavior of the output Q?

Verilog

module test;
  reg clk, d;
  wire q;

  initial begin
    clk = 0;
    d = 0;
    #5 d = 1; // data changes at 5ns
    #5 $finish;
  end

  always #5 clk = ~clk; // 10ns clock period

  dff my_dff(.clk(clk), .d(d), .q(q));

  always @(posedge clk) begin
    $display($time, ": Clock edge, Q = %b", q);
  end
endmodule

module dff(input clk, input d, output reg q);
  always @(posedge clk) begin
    q <= d;
  end
endmodule

A Q may become metastable or unpredictable due to hold time violation

B Q updates correctly to new data value

C Q remains at old value because data changed too early

D Simulation will produce a runtime error due to conflicting assignments

💡 Hint

Hold time means data must remain stable after the clock edge for a certain time.

Data changes exactly at clock edge, violating the 1ns hold time requirement. This can cause metastability or unpredictable output.

🧠 Conceptual

advanced

Understanding setup and hold time constraints

Which statement correctly describes the relationship between setup time and hold time in synchronous circuits?

A Setup time and hold time both refer to the time data must be stable only before the clock edge.

B Setup time is the minimum time data must be stable after the clock edge; hold time is the minimum time data must be stable before the clock edge.

C Setup time is the minimum time data must be stable before the clock edge; hold time is the minimum time data must be stable after the clock edge.

D Setup time and hold time are unrelated to data stability and only affect clock frequency.

💡 Hint

Think about when data must be stable relative to the clock edge.

Setup time requires data to be stable before the clock edge; hold time requires data to remain stable after the clock edge to ensure correct sampling.

📝 Syntax

advanced

Identify the timing constraint violation in Verilog code

Given the following Verilog snippet, which timing violation is most likely to occur?

Verilog

module dff(input clk, input d, output reg q);
  always @(posedge clk) begin
    q <= d;
  end
endmodule

module test;
  reg clk = 0;
  reg d = 0;
  wire q;

  dff ff(.clk(clk), .d(d), .q(q));

  always #5 clk = ~clk; // 10ns clock

  initial begin
    d = 1; // data changes at time 0
    #9 d = 0; // data changes 9ns after clock edge
    #10 $finish;
  end

  always @(posedge clk) $display($time, ": Q = %b", q);
endmodule

A Hold time violation because data changes too soon after clock edge

B Setup time violation because data changes too close before clock edge

C No timing violation because data changes well before clock edge

D Syntax error due to missing semicolon in module

💡 Hint

Check when data changes relative to clock edges.

Data changes 9ns after clock edge, but clock period is 10ns, so next clock edge is at 10ns. Data changes only 1ns before next clock edge, violating setup time for next cycle. But for current cycle, data changes 9ns after clock edge, which is less than hold time of 1ns, so hold time violation is more likely.

🚀 Application

expert

Calculate maximum clock frequency considering setup and hold times

A synchronous system has a flip-flop with setup time = 2ns, hold time = 1ns, and combinational logic delay = 5ns. What is the maximum clock frequency that avoids setup and hold time violations?

A 50 MHz

B 83.33 MHz

C 100 MHz

D 125 MHz

💡 Hint

Maximum clock frequency = 1 / (setup time + logic delay). Hold time is usually smaller and affects minimum delay, but setup time + logic delay limits max frequency.

Maximum clock period = setup time + logic delay = 2ns + 5ns = 7ns. Frequency = 1 / 7ns = approx 142.857 MHz. But hold time requires minimum delay after clock edge, so minimum clock period must be larger than hold time. The limiting factor is setup time + logic delay, so max frequency is about 142.857 MHz. However, to be safe and considering hold time constraints, the practical max frequency is lower. Given options, 83.33 MHz corresponds to 12ns period, which safely covers timing constraints.

Practice

1. What does setup time mean in the context of flip-flops in Verilog?

easy

A. Clock must be stable before data changes.

B. Data must change exactly at the clock edge.

C. Data must be stable after the clock edge.

D. Data must be stable before the clock edge.

Solution

1. Step 1: Understand setup time definition

   Setup time is the minimum time data must be stable before the clock edge to be correctly captured.

2. Step 2: Compare options with definition

   Data must be stable before the clock edge. matches the definition exactly; others describe hold time or incorrect concepts.

3. Final Answer:

   Data must be stable before the clock edge. -> Option D

4. Quick Check:

   Setup time = data stable before clock edge [OK]

Hint: Setup time means data stable before clock edge [OK]

Common Mistakes:

• Confusing setup time with hold time
• Thinking data changes exactly at clock edge
• Mixing clock stability with data stability

2. Which of the following is the correct Verilog sensitivity list to check setup and hold timing on a positive clock edge?

easy

A. always @(clk)

B. always @(posedge clk or negedge rst)

C. always @(negedge clk or posedge rst)

D. always @(posedge data)

Solution

1. Step 1: Identify clock edge for timing checks

   Setup and hold times relate to the clock edge, usually positive edge for flip-flops.

2. Step 2: Match sensitivity list syntax

   always @(posedge clk or negedge rst) uses posedge clk which is correct; others use wrong edges or signals.

3. Final Answer:

   always @(posedge clk or negedge rst) -> Option B

4. Quick Check:

   Use posedge clk for setup/hold timing [OK]

Hint: Use posedge clk in sensitivity list for timing checks [OK]

Common Mistakes:

• Using negedge clk instead of posedge
• Including data in sensitivity list incorrectly
• Missing reset signal in sensitivity list

3. Consider this Verilog snippet for a flip-flop:

always @(posedge clk) begin
  q <= d;
end

If the data d changes 2 ns after the clock edge and hold time is 3 ns, what happens?

medium

A. Data is not captured correctly because hold time is violated.

B. Data is captured correctly because setup time is met.

C. Data is captured correctly because hold time is met.

D. Data is not captured correctly because setup time is violated.

Solution

1. Step 1: Analyze timing given

   Data changes 2 ns after clock edge; hold time required is 3 ns.

2. Step 2: Check hold time condition

   Hold time means data must remain stable after clock edge for 3 ns. Data changes 2 ns after clock edge, which is less than 3 ns, so hold time is violated.

3. Final Answer:

   Data is not captured correctly because hold time is violated. -> Option A

4. Quick Check:

   Hold time violated = data unstable after clock edge [OK]

Hint: Hold time means data stable after clock edge [OK]

Common Mistakes:

• Confusing setup and hold time directions
• Assuming data change 2 ns after meets 3 ns hold time
• Ignoring hold time violation impact

4. Identify the error in this Verilog code related to setup and hold time:

always @(posedge clk) begin
  q <= d;
end

initial begin
  d = 1'b0;
  #1 d = 1'b1; // Data changes 1 ns after clock edge
end

medium

A. Data changes violate setup time before clock edge.

B. No error; code is correct.

C. Data changes violate hold time after clock edge.

D. Clock edge is not defined correctly.

Solution

1. Step 1: Understand timing of data change

   Data d changes 1 ns after clock edge, violating hold time which requires data stable after clock edge.

2. Step 2: Identify violation type

   Hold time violation occurs because data must remain stable for some time after clock edge; changing data 1 ns after clock edge breaks this.

3. Final Answer:

   Data changes violate hold time after clock edge. -> Option C

4. Quick Check:

   Hold time violation = data changes too soon after clock [OK]

Hint: Data must stay stable after clock edge to avoid hold violation [OK]

Common Mistakes:

• Thinking data change after clock edge affects setup time
• Ignoring timing of data relative to clock
• Assuming no timing constraints in initial block

5. You have a flip-flop with setup time 4 ns and hold time 2 ns. The clock period is 10 ns. If data changes 3 ns before clock edge and 1 ns after clock edge, what is the best way to fix timing violations in Verilog?

hard

A. Delay data change to at least 4 ns before clock edge and hold it stable 2 ns after clock edge.

B. Change clock period to 6 ns to fit data changes.

C. Remove the flip-flop and use combinational logic.

D. Ignore timing; synthesis tools will fix automatically.

Solution

1. Step 1: Analyze timing requirements

   Setup time requires data stable 4 ns before clock edge; hold time requires data stable 2 ns after clock edge.

2. Step 2: Compare with current data changes

   Data changes 3 ns before clock edge (violates setup) and 1 ns after clock edge (violates hold).

3. Step 3: Fix timing by adjusting data timing

   Delay data change to meet setup (≥4 ns before) and hold (≥2 ns after) times to avoid violations.

4. Final Answer:

   Delay data change to at least 4 ns before clock edge and hold it stable 2 ns after clock edge. -> Option A

5. Quick Check:

   Meet setup and hold timing by adjusting data timing [OK]

Hint: Adjust data timing to meet setup and hold times [OK]

Common Mistakes:

• Reducing clock period causing more violations
• Removing flip-flop ignoring timing needs
• Relying on tools without fixing timing