Resource sharing and area optimization in Verilog - Mini Project: Build & Apply

Resource sharing and area optimization

📖 Scenario: You are designing a simple digital circuit that performs arithmetic operations. To save space on the chip, you want to share hardware resources instead of duplicating them.

🎯 Goal: Build a Verilog module that uses resource sharing to perform addition and subtraction using a single adder/subtractor unit, optimizing the area.

📋 What You'll Learn

Create a Verilog module with two 4-bit inputs and one control input

Use a single adder/subtractor unit to perform addition or subtraction based on the control input

Output the 4-bit result

Use resource sharing to minimize hardware usage

💡 Why This Matters

🌍 Real World

Resource sharing in hardware design helps reduce chip area and cost by reusing components for multiple functions.

💼 Career

Understanding resource sharing is important for FPGA and ASIC designers to optimize digital circuits efficiently.

1

Create inputs and outputs

Create a Verilog module called arith_unit with two 4-bit inputs named a and b, one 1-bit input named sub to select subtraction when high, and one 4-bit output named result.

Verilog

module arith_unit(
    input [3:0] a,
    input [3:0] b,
    input sub,
    output [3:0] result
);

// Your code here

endmodule

Hint

Define the module and declare inputs and outputs exactly as specified.

2

Add a wire for modified input

Inside the arith_unit module, declare a 4-bit wire named b_mod that will hold the modified value of b for subtraction. Also declare a 1-bit wire named carry_in that will be 1 when sub is high and 0 otherwise.

Verilog

module arith_unit(
    input [3:0] a,
    input [3:0] b,
    input sub,
    output [3:0] result
);

wire [3:0] b_mod;
wire carry_in;
// Your code here

endmodule

Hint

Use bitwise XOR to invert b when sub is 1, and set carry_in equal to sub.

3

Implement the adder/subtractor logic

Inside the arith_unit module, declare a 5-bit wire named sum to hold the addition result including carry. Use the Verilog addition operator to add a, b_mod, and carry_in. Assign the lower 4 bits of sum to the output result.

Verilog

module arith_unit(
    input [3:0] a,
    input [3:0] b,
    input sub,
    output [3:0] result
);

wire [3:0] b_mod;
wire carry_in;
wire [4:0] sum;

assign b_mod = b ^ {4{sub}};
assign carry_in = sub;

// Your code here

endmodule

Hint

Add a, b_mod, and carry_in and assign the lower 4 bits to result.

4

Test the module output

Write a testbench code that instantiates arith_unit and prints the result for inputs a = 4'b0110, b = 4'b0011 with sub = 0 (addition) and then with sub = 1 (subtraction). Use $display to show the results.

Verilog

module testbench;
reg [3:0] a, b;
reg sub;
wire [3:0] result;

arith_unit uut(.a(a), .b(b), .sub(sub), .result(result));

initial begin
    a = 4'b0110;
    b = 4'b0011;
    sub = 0;
    #1;
    // Your code here
end
endmodule

Hint

Set inputs, wait a moment, then display result for both sub=0 and sub=1.

Practice

1. What is the main goal of resource sharing in Verilog designs?

easy

A. To make the code more complex and harder to read

B. To increase the clock speed of the design

C. To add more hardware components for better performance

D. To use the same hardware for multiple tasks to save space

Solution

1. Step 1: Understand resource sharing concept and main benefit

   Resource sharing means using one hardware block for different tasks instead of multiple blocks. This reduces the total hardware area, saving space and cost.

2. Final Answer:

   To use the same hardware for multiple tasks to save space -> Option D

3. Quick Check:

   Resource sharing = save space [OK]

Hint: Resource sharing means reusing hardware to save space [OK]

Common Mistakes:

• Thinking resource sharing always increases speed
• Confusing resource sharing with adding more hardware
• Believing resource sharing makes code more complex

2. Which Verilog construct is commonly used to implement resource sharing for arithmetic operations?

easy

A. A single always block with a shared adder and multiplexers

B. Instantiating multiple modules for each arithmetic unit

C. Using multiple assign statements for each operation

D. Multiple always blocks with separate adders

Solution

1. Step 1: Identify resource sharing method and Verilog construct

   Resource sharing uses one hardware unit shared by multiple operations, controlled by multiplexers. A single always block with a shared adder and multiplexers allows selecting inputs dynamically.

2. Final Answer:

   A single always block with a shared adder and multiplexers -> Option A

3. Quick Check:

   Shared adder + mux = resource sharing [OK]

Hint: Use multiplexers to select inputs for shared hardware [OK]

Common Mistakes:

• Using multiple adders instead of sharing one
• Not using multiplexers to control input selection
• Instantiating separate modules unnecessarily

3. Consider the following Verilog snippet for resource sharing:

reg [3:0] a, b, c, result;
reg sel;
always @(*) begin
  case(sel)
    1'b0: result = a + b;
    1'b1: result = b + c;
  endcase
end

What is the output in result when a=4, b=3, c=5, and sel=1?

medium

A. 8

B. 5

C. 7

D. Syntax error

Solution

1. Step 1: Understand case selection and calculate

   When sel=1, result = b + c. b=3 and c=5, so result = 3 + 5 = 8.

2. Final Answer:

   8 -> Option A

3. Quick Check:

   sel=1 means result = b+c = 8 [OK]

Hint: Check sel value to pick correct operation [OK]

Common Mistakes:

• Adding a + b instead of b + c when sel=1
• Confusing variable values
• Assuming syntax error due to case statement

4. Identify the error in this Verilog code snippet intended for resource sharing:

reg [7:0] x, y, z;
reg sel;
always @(posedge clk) begin
  if(sel == 0)
    z = x + y;
  else
    z = x - y;
end

medium

A. Missing sensitivity list for combinational logic

B. Using blocking assignment (=) inside a clocked always block

C. Incorrect use of if-else statement

D. No error, code is correct

Solution

1. Step 1: Check assignment type and identify error

   Inside a clocked always block, non-blocking assignment (<=) should be used for registers. The code uses blocking assignment (=), which can cause simulation mismatches and timing issues.

2. Final Answer:

   Using blocking assignment (=) inside a clocked always block -> Option B

3. Quick Check:

   Clocked block needs <=, not = [OK]

Hint: Use <= in clocked always blocks for registers [OK]

Common Mistakes:

• Using = instead of <= in sequential logic
• Confusing sensitivity list for clocked blocks
• Thinking if-else is incorrect syntax

5. You want to optimize area by sharing a multiplier between two operations in a Verilog design. Which approach best balances area saving and performance?

hard

A. Use combinational logic to duplicate multiplier outputs without sharing hardware

B. Instantiate two separate multipliers to run operations in parallel

C. Use one multiplier with a multiplexer to select inputs and schedule operations sequentially

D. Replace multiplier with addition to save area

Solution

1. Step 1: Understand trade-off and identify best approach

   Sharing one multiplier saves area but may reduce speed due to sequential operation. Using one multiplier with multiplexers and scheduling operations sequentially balances area saving and acceptable performance.

2. Final Answer:

   Use one multiplier with a multiplexer to select inputs and schedule operations sequentially -> Option C

3. Quick Check:

   Shared multiplier + mux + scheduling = area optimization [OK]

Hint: Share hardware with mux and schedule operations sequentially [OK]

Common Mistakes:

• Using multiple multipliers wastes area
• Duplicating outputs without sharing hardware
• Replacing multiplier with addition changes functionality