Resource sharing and area optimization in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of resource sharing in combinational logic

What is the output of the following Verilog module when a = 3 and b = 2?

Verilog

module resource_share(input [3:0] a, input [3:0] b, output [7:0] y);
  wire [7:0] temp1, temp2;
  assign temp1 = a * 2;
  assign temp2 = b * 2;
  assign y = temp1 + temp2;
endmodule

// Inputs: a=3, b=2

A 5

B 12

C 8

D 10

💡 Hint

Calculate each multiplication and then add the results.

temp1 = 3 * 2 = 6, temp2 = 2 * 2 = 4, so y = 6 + 4 = 10.

🧠 Conceptual

intermediate

Effect of resource sharing on area

Which statement best describes how resource sharing affects the area of a digital design?

A Resource sharing reduces area by reusing hardware blocks for multiple operations.

B Resource sharing increases area because it duplicates hardware blocks.

C Resource sharing has no effect on area but improves speed.

D Resource sharing only affects power consumption, not area.

💡 Hint

Think about using one hardware block for several tasks instead of many blocks.

Resource sharing reduces area by allowing the same hardware to perform multiple operations at different times, avoiding duplication.

🔧 Debug

advanced

Identify the error in resource sharing implementation

What error will occur when synthesizing the following Verilog code that attempts resource sharing?

Verilog

module shared_multiplier(input clk, input [3:0] x, input [3:0] y, input sel, output reg [7:0] result);
  reg [7:0] mul1, mul2;
  always @(posedge clk) begin
    mul1 <= x * 2;
    mul2 <= y * 3;
    if (sel)
      result <= mul1;
    else
      result <= mul2;
  end
endmodule

A No error; code synthesizes correctly.

B Synthesis error because multiplication is not allowed in always block.

C Result may be incorrect due to simultaneous updates of mul1 and mul2 causing race conditions.

D Result will always be zero because registers are not initialized.

💡 Hint

Consider how mul1 and mul2 update and how result selects between them.

mul1 and mul2 update simultaneously on clock edge, but result selects one based on sel. If sel changes asynchronously, result may latch incorrect value due to timing.

📝 Syntax

advanced

Syntax correctness in resource sharing code

Which option contains the correct Verilog syntax for sharing a single adder between two operations using a multiplexer?

A assign sum = (sel) ? a + b : c + d;

B assign sum = sel ? (a + b) : (c + d);

C ;d + c : b + a ? les = mus ngissa

D assign sum = sel ? a + b : c + d;

💡 Hint

Check operator precedence and parentheses usage.

Option B correctly uses parentheses to ensure addition happens before the conditional operator selects the result.

🚀 Application

expert

Calculate area reduction from resource sharing

A design uses two separate multipliers each occupying 100 units of area. By sharing one multiplier between two operations using multiplexing, the total multiplier area reduces. If the multiplexer and control logic add 20 units of area, what is the total area after resource sharing?

A 120 units

B 200 units

C 220 units

D 80 units

💡 Hint

Calculate area of one multiplier plus added multiplexing logic.

Sharing reduces two multipliers (2 x 100 = 200) to one multiplier (100) plus 20 units for multiplexing, total 120 units.

Practice

1. What is the main goal of resource sharing in Verilog designs?

easy

A. To make the code more complex and harder to read

B. To increase the clock speed of the design

C. To add more hardware components for better performance

D. To use the same hardware for multiple tasks to save space

Solution

1. Step 1: Understand resource sharing concept and main benefit

   Resource sharing means using one hardware block for different tasks instead of multiple blocks. This reduces the total hardware area, saving space and cost.

2. Final Answer:

   To use the same hardware for multiple tasks to save space -> Option D

3. Quick Check:

   Resource sharing = save space [OK]

Hint: Resource sharing means reusing hardware to save space [OK]

Common Mistakes:

• Thinking resource sharing always increases speed
• Confusing resource sharing with adding more hardware
• Believing resource sharing makes code more complex

2. Which Verilog construct is commonly used to implement resource sharing for arithmetic operations?

easy

A. A single always block with a shared adder and multiplexers

B. Instantiating multiple modules for each arithmetic unit

C. Using multiple assign statements for each operation

D. Multiple always blocks with separate adders

Solution

1. Step 1: Identify resource sharing method and Verilog construct

   Resource sharing uses one hardware unit shared by multiple operations, controlled by multiplexers. A single always block with a shared adder and multiplexers allows selecting inputs dynamically.

2. Final Answer:

   A single always block with a shared adder and multiplexers -> Option A

3. Quick Check:

   Shared adder + mux = resource sharing [OK]

Hint: Use multiplexers to select inputs for shared hardware [OK]

Common Mistakes:

• Using multiple adders instead of sharing one
• Not using multiplexers to control input selection
• Instantiating separate modules unnecessarily

3. Consider the following Verilog snippet for resource sharing:

reg [3:0] a, b, c, result;
reg sel;
always @(*) begin
  case(sel)
    1'b0: result = a + b;
    1'b1: result = b + c;
  endcase
end

What is the output in result when a=4, b=3, c=5, and sel=1?

medium

A. 8

B. 5

C. 7

D. Syntax error

Solution

1. Step 1: Understand case selection and calculate

   When sel=1, result = b + c. b=3 and c=5, so result = 3 + 5 = 8.

2. Final Answer:

   8 -> Option A

3. Quick Check:

   sel=1 means result = b+c = 8 [OK]

Hint: Check sel value to pick correct operation [OK]

Common Mistakes:

• Adding a + b instead of b + c when sel=1
• Confusing variable values
• Assuming syntax error due to case statement

4. Identify the error in this Verilog code snippet intended for resource sharing:

reg [7:0] x, y, z;
reg sel;
always @(posedge clk) begin
  if(sel == 0)
    z = x + y;
  else
    z = x - y;
end

medium

A. Missing sensitivity list for combinational logic

B. Using blocking assignment (=) inside a clocked always block

C. Incorrect use of if-else statement

D. No error, code is correct

Solution

1. Step 1: Check assignment type and identify error

   Inside a clocked always block, non-blocking assignment (<=) should be used for registers. The code uses blocking assignment (=), which can cause simulation mismatches and timing issues.

2. Final Answer:

   Using blocking assignment (=) inside a clocked always block -> Option B

3. Quick Check:

   Clocked block needs <=, not = [OK]

Hint: Use <= in clocked always blocks for registers [OK]

Common Mistakes:

• Using = instead of <= in sequential logic
• Confusing sensitivity list for clocked blocks
• Thinking if-else is incorrect syntax

5. You want to optimize area by sharing a multiplier between two operations in a Verilog design. Which approach best balances area saving and performance?

hard

A. Use combinational logic to duplicate multiplier outputs without sharing hardware

B. Instantiate two separate multipliers to run operations in parallel

C. Use one multiplier with a multiplexer to select inputs and schedule operations sequentially

D. Replace multiplier with addition to save area

Solution

1. Step 1: Understand trade-off and identify best approach

   Sharing one multiplier saves area but may reduce speed due to sequential operation. Using one multiplier with multiplexers and scheduling operations sequentially balances area saving and acceptable performance.

2. Final Answer:

   Use one multiplier with a multiplexer to select inputs and schedule operations sequentially -> Option C

3. Quick Check:

   Shared multiplier + mux + scheduling = area optimization [OK]

Hint: Share hardware with mux and schedule operations sequentially [OK]

Common Mistakes:

• Using multiple multipliers wastes area
• Duplicating outputs without sharing hardware
• Replacing multiplier with addition changes functionality