Pulse generator in Verilog - Step-by-Step Execution

Concept Flow - Pulse generator

Start

↓

Wait for clock edge

↓

Check if reset

↓

Set output=0

↓

Wait next clock

↓

Set output=0

↓

Repeat

The pulse generator waits for a clock edge, sets output high for one clock cycle, then sets it low, repeating this cycle.

Execution Sample

Verilog

module pulse_gen(
  input clk, reset,
  output reg pulse
);
always @(posedge clk or posedge reset) begin
  if (reset) pulse <= 0;
  else pulse <= ~pulse;
end
endmodule

This code toggles the pulse output on each clock cycle, resetting it to 0 when reset is high.

Execution Table

Step	clk	reset	pulse before	Condition	pulse after	Notes
1	0	1	x	reset=1	0	Reset active, pulse set to 0
2	1	0	0	reset=0	1	Clock rising edge, pulse toggles to 1
3	0	0	1	No posedge clk	1	No change, waiting for clock rising edge
4	1	0	1	reset=0	0	Clock rising edge, pulse toggles to 0
5	0	0	0	No posedge clk	0	No change, waiting for clock rising edge
6	1	0	0	reset=0	1	Clock rising edge, pulse toggles to 1
Exit	-	-	-	Simulation end	-	End of trace

💡 Simulation ends after several clock cycles to show pulse toggling

Variable Tracker

Variable	Start	After Step 1	After Step 2	After Step 4	After Step 6	Final
pulse	x	0	1	0	1	1
clk	0	1	0	1	0	1
reset	1	0	0	0	0	0

Key Moments - 2 Insights

Why does pulse only change on clock rising edges?

Because the always block triggers only on posedge clk or posedge reset, pulse updates only at those times (see steps 2,4,6).

What happens to pulse when reset is high?

Pulse is immediately set to 0 regardless of clock, as shown in step 1.

Visual Quiz - 3 Questions

Look at the execution table, what is the value of pulse after step 2?

A 0

B 1

C x

D unchanged

💡 Hint

Check the 'pulse after' column in row for step 2.

At which step does reset cause pulse to be set to 0?

A Step 2

B Step 4

C Step 1

D Step 6

💡 Hint

Look for reset=1 condition in the execution table.

If reset stayed high, what would pulse be after step 6?

A 0

B toggles every clock

C 1

D undefined

💡 Hint

Reset forces pulse to 0 immediately, see step 1 behavior.

Concept Snapshot

Pulse generator in Verilog:
- Use always @(posedge clk or posedge reset)
- On reset, set pulse=0
- Else toggle pulse each clock
- Output is a 1-cycle pulse toggling every clock
- Useful for timing signals and triggers

Full Transcript

This visual trace shows a Verilog pulse generator module. The pulse output resets to 0 when reset is high. On each rising clock edge, pulse toggles between 0 and 1. The execution table tracks clock, reset, and pulse values step-by-step. Pulse changes only on clock rising edges or reset. This helps beginners see how hardware signals update over time in a simple pulse generator.

Practice

1. What is the main purpose of a pulse generator in Verilog?

easy

A. To convert analog signals to digital

B. To store large amounts of data

C. To perform arithmetic calculations

D. To create short on/off signals in digital circuits

Solution

1. Step 1: Understand the function of a pulse generator

   A pulse generator creates short bursts of signals that switch between high and low states.

2. Step 2: Compare options with the definition

   Only To create short on/off signals in digital circuits describes creating short on/off signals, which matches the pulse generator's role.

3. Final Answer:

   To create short on/off signals in digital circuits -> Option D

4. Quick Check:

   Pulse generator = short on/off signals [OK]

Hint: Pulse generator makes quick on/off signals [OK]

Common Mistakes:

• Confusing pulse generator with memory storage
• Thinking it performs calculations
• Mixing it up with analog to digital converters

2. Which of the following is the correct way to declare a 4-bit counter register in Verilog?

easy

A. reg counter[3:0];

B. wire [4:0] counter;

C. reg [3:0] counter;

D. integer counter = 4;

Solution

1. Step 1: Recall Verilog register declaration syntax

   Registers use 'reg' keyword and bit width is declared as [high:low].

2. Step 2: Check each option

   reg [3:0] counter; correctly declares a 4-bit register from bit 3 down to 0. wire [4:0] counter; uses 'wire' which is not for registers. reg counter[3:0]; uses incorrect array syntax. integer counter = 4; declares an integer, not a 4-bit register.

3. Final Answer:

   reg [3:0] counter; -> Option C

4. Quick Check:

   4-bit reg = reg [3:0] name; [OK]

Hint: Use reg [3:0] for 4-bit registers [OK]

Common Mistakes:

• Using wire instead of reg for counters
• Incorrect bit range syntax
• Confusing arrays with bit vectors

3. Given this Verilog code snippet for a pulse generator:

reg [3:0] count = 0;
reg pulse = 0;
always @(posedge clk or posedge reset) begin
  if (reset) begin
    count <= 0;
    pulse <= 0;
  end else if (count == 4) begin
    pulse <= 1;
    count <= 0;
  end else begin
    pulse <= 0;
    count <= count + 1;
  end
end

What will be the value of pulse after 5 clock cycles without reset?

medium

A. 0

B. 1

C. Undefined

D. It causes a syntax error

Solution

1. Step 1: Trace the counter and pulse values over clock cycles

   Count starts at 0. Each clock cycle increments count by 1 until it reaches 4. At count == 4, pulse is set to 1 and count resets to 0.

2. Step 2: Determine pulse value at 5th clock

   At 5th clock, count was 4, so pulse becomes 1.

3. Final Answer:

   1 -> Option B

4. Quick Check:

   Pulse high at count 4 = 1 [OK]

Hint: Pulse goes high when count hits 4 [OK]

Common Mistakes:

• Assuming pulse stays high after count resets
• Confusing reset behavior
• Ignoring the else conditions

4. Identify the error in this pulse generator code snippet:

reg [3:0] count;
reg pulse;
always @(posedge clk) begin
  if (reset) begin
    count = 0;
    pulse = 0;
  end else if (count == 4) begin
    pulse = 1;
    count = 0;
  end else begin
    pulse = 0;
    count = count + 1;
  end
end

medium

A. Using blocking assignments (=) inside always @(posedge clk)

B. Missing sensitivity to reset signal

C. Incorrect bit width for count register

D. pulse should be declared as wire, not reg

Solution

1. Step 1: Check assignment types in sequential always block

   Inside always @(posedge clk), non-blocking assignments (<=) should be used to avoid race conditions.

2. Step 2: Identify the error

   The code uses blocking assignments (=) which is incorrect for sequential logic.

3. Final Answer:

   Using blocking assignments (=) inside always @(posedge clk) -> Option A

4. Quick Check:

   Sequential logic uses <=, not = [OK]

Hint: Use <= in clocked always blocks [OK]

Common Mistakes:

• Using = instead of <= in sequential blocks
• Not including reset in sensitivity list
• Declaring pulse as wire instead of reg

5. You want to design a pulse generator that produces a high pulse for exactly 3 clock cycles every 10 clock cycles. Which approach correctly implements this behavior?

hard

A. Use a 4-bit counter that resets at 10, set pulse high when count < 3

B. Use a 3-bit counter that resets at 3, pulse high when count == 10

C. Use a 4-bit counter that resets at 3, pulse high when count > 10

D. Use a 10-bit counter that resets at 3, pulse high when count == 3

Solution

1. Step 1: Understand the timing requirements

   The pulse should be high for 3 cycles and repeat every 10 cycles, so count cycles from 0 to 9.

2. Step 2: Choose counter and pulse logic

   A 4-bit counter can count up to 15, enough for 10 cycles. Setting pulse high when count is less than 3 gives a 3-cycle pulse.

3. Final Answer:

   Use a 4-bit counter that resets at 10, set pulse high when count < 3 -> Option A

4. Quick Check:

   Pulse high 3 cycles every 10 cycles = Use a 4-bit counter that resets at 10, set pulse high when count < 3 [OK]

Hint: Pulse high when count < pulse width, reset at total cycles [OK]

Common Mistakes:

• Using wrong counter size
• Setting pulse high at wrong count values
• Confusing reset and pulse conditions