Pulse generator in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output pulse width in clock cycles?

Given this Verilog pulse generator module, what is the width of the output pulse pulse_out in clock cycles?

Verilog

module pulse_gen(input clk, input trigger, output reg pulse_out);
  reg [3:0] count;
  always @(posedge clk) begin
    if (trigger) count <= 4'd5;
    else if (count != 0) count <= count - 1;
    pulse_out <= (count != 0);
  end
endmodule

A 4 clock cycles

B 1 clock cycle

C 5 clock cycles

D 6 clock cycles

💡 Hint

Count starts at 5 and decrements each clock cycle while pulse_out is high.

The counter is set to 5 when triggered and counts down to 0. The pulse_out stays high while count is not zero, so it lasts 5 clock cycles.

🧠 Conceptual

intermediate

What is the role of the 'posedge clk' in the pulse generator?

In a pulse generator module, why do we use always @(posedge clk) instead of always @(clk)?

A To trigger the block only on the rising edge of the clock, ensuring synchronous operation.

B To trigger the block on both rising and falling edges of the clock.

C To trigger the block asynchronously whenever the clock changes.

D To trigger the block only when the clock is low.

💡 Hint

Think about how synchronous digital circuits work with clock edges.

Using posedge clk triggers the block only on the rising edge, which is standard for synchronous designs to avoid glitches and ensure predictable timing.

🔧 Debug

advanced

What is the length of the pulse generated by this pulse generator?

Consider this Verilog code snippet for a pulse generator:

module pulse_gen(input clk, input trigger, output reg pulse_out);
  reg [2:0] count;
  always @(posedge clk) begin
    if (trigger) count <= 3'd4;
    else if (count > 0) count <= count - 1;
    pulse_out <= (count > 0);
  end
endmodule

What is the length of the pulse generated after trigger is asserted?

A 1 clock cycle, because count resets immediately after trigger.

B 3 clock cycles, because the pulse_out is high only while count is greater than zero, starting from 4 but counting down to 1.

C 5 clock cycles, because the count includes zero as a pulse cycle.

D 4 clock cycles, because count starts at 4 and pulse_out is high while count > 0.

💡 Hint

Trace the count values and when pulse_out is high.

After the trigger clock (where count <= 4 but pulse_out uses prior count > 0 which is false), pulse_out goes high for the next four cycles: count=4 (high, dec to 3), 3 (high, to 2), 2 (high, to 1), 1 (high, to 0).

📝 Syntax

advanced

Which option causes a syntax error in this pulse generator code?

Identify which code snippet will cause a syntax error when synthesizing a pulse generator in Verilog.

A always @(posedge clk) begin if(trigger) count <= 4'd5; else if(count != 0) count <= count - 1; pulse_out <= (count != 0); end

B always @(posedge clk) begin if(trigger) count <= 4'd5 else if(count != 0) count <= count - 1; pulse_out <= (count != 0); end

C always @(posedge clk) begin if(trigger) count = 4'd5; else if(count != 0) count = count - 1; pulse_out = (count != 0); end

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💡 Hint

Look carefully for missing punctuation in the code.

Option B is missing a semicolon after count <= 4'd5, causing a syntax error.

🚀 Application

expert

How to generate a single pulse on trigger with a parameterized width?

You want to design a Verilog module that outputs a single pulse of a width defined by a parameter PULSE_WIDTH when a trigger input goes high. Which code snippet correctly implements this behavior?

A

module pulse_gen #(parameter PULSE_WIDTH = 8) (input clk, input trigger, output reg pulse_out);
  reg [$clog2(PULSE_WIDTH):0] count;
  always @(posedge clk) begin
    if(trigger) count <= PULSE_WIDTH;
    else if(count > 0) count <= count - 1;
    pulse_out <= (count > 0);
  end
endmodule

B

module pulse_gen #(parameter PULSE_WIDTH = 8) (input clk, input trigger, output reg pulse_out);
  reg [$clog2(PULSE_WIDTH):0] count;
  always @(posedge clk) begin
    if(trigger) count <= PULSE_WIDTH - 1;
    else if(count > 0) count <= count - 1;
    pulse_out <= (count > 0);
  end
endmodule

C

module pulse_gen #(parameter PULSE_WIDTH = 8) (input clk, input trigger, output reg pulse_out);
  reg [$clog2(PULSE_WIDTH):0] count;
  always @(posedge clk) begin
    if(trigger) count <= PULSE_WIDTH;
    else if(count != 0) count <= count - 1;
    pulse_out <= (count != 0);
  end
endmodule

D

module pulse_gen #(parameter PULSE_WIDTH = 8) (input clk, input trigger, output reg pulse_out);
  reg [$clog2(PULSE_WIDTH):0] count;
  always @(posedge clk) begin
    if(trigger) count <= PULSE_WIDTH;
    else if(count != 0) count <= count - 1;
    pulse_out <= (count > 0);
  end
endmodule

💡 Hint

Check how the count is initialized and how pulse_out is assigned to get the exact pulse width.

Option A correctly sets count to PULSE_WIDTH and decrements while count > 0, with pulse_out high while count > 0, producing a pulse of exactly PULSE_WIDTH clock cycles.

Practice

1. What is the main purpose of a pulse generator in Verilog?

easy

A. To convert analog signals to digital

B. To store large amounts of data

C. To perform arithmetic calculations

D. To create short on/off signals in digital circuits

Solution

1. Step 1: Understand the function of a pulse generator

   A pulse generator creates short bursts of signals that switch between high and low states.

2. Step 2: Compare options with the definition

   Only To create short on/off signals in digital circuits describes creating short on/off signals, which matches the pulse generator's role.

3. Final Answer:

   To create short on/off signals in digital circuits -> Option D

4. Quick Check:

   Pulse generator = short on/off signals [OK]

Hint: Pulse generator makes quick on/off signals [OK]

Common Mistakes:

• Confusing pulse generator with memory storage
• Thinking it performs calculations
• Mixing it up with analog to digital converters

2. Which of the following is the correct way to declare a 4-bit counter register in Verilog?

easy

A. reg counter[3:0];

B. wire [4:0] counter;

C. reg [3:0] counter;

D. integer counter = 4;

Solution

1. Step 1: Recall Verilog register declaration syntax

   Registers use 'reg' keyword and bit width is declared as [high:low].

2. Step 2: Check each option

   reg [3:0] counter; correctly declares a 4-bit register from bit 3 down to 0. wire [4:0] counter; uses 'wire' which is not for registers. reg counter[3:0]; uses incorrect array syntax. integer counter = 4; declares an integer, not a 4-bit register.

3. Final Answer:

   reg [3:0] counter; -> Option C

4. Quick Check:

   4-bit reg = reg [3:0] name; [OK]

Hint: Use reg [3:0] for 4-bit registers [OK]

Common Mistakes:

• Using wire instead of reg for counters
• Incorrect bit range syntax
• Confusing arrays with bit vectors

3. Given this Verilog code snippet for a pulse generator:

reg [3:0] count = 0;
reg pulse = 0;
always @(posedge clk or posedge reset) begin
  if (reset) begin
    count <= 0;
    pulse <= 0;
  end else if (count == 4) begin
    pulse <= 1;
    count <= 0;
  end else begin
    pulse <= 0;
    count <= count + 1;
  end
end

What will be the value of pulse after 5 clock cycles without reset?

medium

A. 0

B. 1

C. Undefined

D. It causes a syntax error

Solution

1. Step 1: Trace the counter and pulse values over clock cycles

   Count starts at 0. Each clock cycle increments count by 1 until it reaches 4. At count == 4, pulse is set to 1 and count resets to 0.

2. Step 2: Determine pulse value at 5th clock

   At 5th clock, count was 4, so pulse becomes 1.

3. Final Answer:

   1 -> Option B

4. Quick Check:

   Pulse high at count 4 = 1 [OK]

Hint: Pulse goes high when count hits 4 [OK]

Common Mistakes:

• Assuming pulse stays high after count resets
• Confusing reset behavior
• Ignoring the else conditions

4. Identify the error in this pulse generator code snippet:

reg [3:0] count;
reg pulse;
always @(posedge clk) begin
  if (reset) begin
    count = 0;
    pulse = 0;
  end else if (count == 4) begin
    pulse = 1;
    count = 0;
  end else begin
    pulse = 0;
    count = count + 1;
  end
end

medium

A. Using blocking assignments (=) inside always @(posedge clk)

B. Missing sensitivity to reset signal

C. Incorrect bit width for count register

D. pulse should be declared as wire, not reg

Solution

1. Step 1: Check assignment types in sequential always block

   Inside always @(posedge clk), non-blocking assignments (<=) should be used to avoid race conditions.

2. Step 2: Identify the error

   The code uses blocking assignments (=) which is incorrect for sequential logic.

3. Final Answer:

   Using blocking assignments (=) inside always @(posedge clk) -> Option A

4. Quick Check:

   Sequential logic uses <=, not = [OK]

Hint: Use <= in clocked always blocks [OK]

Common Mistakes:

• Using = instead of <= in sequential blocks
• Not including reset in sensitivity list
• Declaring pulse as wire instead of reg

5. You want to design a pulse generator that produces a high pulse for exactly 3 clock cycles every 10 clock cycles. Which approach correctly implements this behavior?

hard

A. Use a 4-bit counter that resets at 10, set pulse high when count < 3

B. Use a 3-bit counter that resets at 3, pulse high when count == 10

C. Use a 4-bit counter that resets at 3, pulse high when count > 10

D. Use a 10-bit counter that resets at 3, pulse high when count == 3

Solution

1. Step 1: Understand the timing requirements

   The pulse should be high for 3 cycles and repeat every 10 cycles, so count cycles from 0 to 9.

2. Step 2: Choose counter and pulse logic

   A 4-bit counter can count up to 15, enough for 10 cycles. Setting pulse high when count is less than 3 gives a 3-cycle pulse.

3. Final Answer:

   Use a 4-bit counter that resets at 10, set pulse high when count < 3 -> Option A

4. Quick Check:

   Pulse high 3 cycles every 10 cycles = Use a 4-bit counter that resets at 10, set pulse high when count < 3 [OK]

Hint: Pulse high when count < pulse width, reset at total cycles [OK]

Common Mistakes:

• Using wrong counter size
• Setting pulse high at wrong count values
• Confusing reset and pulse conditions