Port connection by name vs by position in Verilog - Hands-On Comparison

Port connection by name vs by position

📖 Scenario: You are designing a simple digital circuit using Verilog. You want to understand how to connect module ports by position and by name.

🎯 Goal: Build a Verilog module instantiation example showing port connection by position and by name, and observe the output signals.

📋 What You'll Learn

Create a module called and_gate with two inputs a and b and one output out.

Create signals sig1, sig2, and result.

Instantiate and_gate twice: once connecting ports by position, once by name.

Assign values to sig1 and sig2 and display the output result.

💡 Why This Matters

🌍 Real World

Connecting ports correctly is essential when building complex digital circuits with reusable modules.

💼 Career

Hardware engineers and FPGA designers use port connections by name and position to build and maintain reliable hardware designs.

1

Create the and_gate module

Write a Verilog module called and_gate with inputs a and b and output out. The output out should be the AND of a and b.

Verilog

// Your code here

Hint

Use assign out = a & b; inside the module.

2

Create signals and connect ports by position

Declare reg sig1, reg sig2, and wire result_pos. Instantiate and_gate as and1 connecting ports by position with sig1, sig2, and result_pos.

Verilog

module and_gate(input a, input b, output out);
    assign out = a & b;
endmodule

// Your code here

Hint

Use and_gate and1(sig1, sig2, result_pos); to connect by position.

3

Instantiate and_gate connecting ports by name

Inside the top module, declare wire result_name. Instantiate and_gate as and2 connecting ports by name: connect a to sig1, b to sig2, and out to result_name.

Verilog

module and_gate(input a, input b, output out);
    assign out = a & b;
endmodule

module top;
    reg sig1;
    reg sig2;
    wire result_pos;

    and_gate and1(sig1, sig2, result_pos);

    // Your code here
endmodule

Hint

Use dot notation like .a(sig1) to connect ports by name.

4

Assign values and display outputs

Inside the top module, add an initial block. Assign sig1 = 1 and sig2 = 0. Use $display to print "result_pos = %b, result_name = %b", result_pos, result_name.

Verilog

module and_gate(input a, input b, output out);
    assign out = a & b;
endmodule

module top;
    reg sig1;
    reg sig2;
    wire result_pos;
    wire result_name;

    and_gate and1(sig1, sig2, result_pos);
    and_gate and2(.a(sig1), .b(sig2), .out(result_name));

    // Your code here
endmodule

Hint

Use initial block to assign values and $display to print results.

Practice

1. What is the main difference between port connection by name and port connection by position in Verilog?

easy

A. By position allows skipping ports; by name does not allow skipping ports.

B. By position connects ports explicitly by their names; by name connects ports in the order declared.

C. By name requires fewer ports; by position requires all ports to be connected.

D. By name connects ports explicitly by their names; by position connects ports in the order declared.

Solution

1. Step 1: Understand port connection by position

   Port connection by position links signals to ports based on the order the ports are declared in the module.

2. Step 2: Understand port connection by name

   Port connection by name links signals explicitly by specifying the port names, so order does not matter.

3. Final Answer:

   By name connects ports explicitly by their names; by position connects ports in the order declared. -> Option D

4. Quick Check:

   Port connection by name = explicit naming [OK]

Hint: Remember: name = explicit, position = order [OK]

Common Mistakes:

• Confusing order with explicit naming
• Thinking by position allows skipping ports
• Assuming by name requires fewer ports

2. Which of the following is the correct syntax for connecting ports by name in Verilog?

easy

A. module_name (input_signal, output_signal);

B. module_name (.port1(input_signal), .port2(output_signal));

C. module_name {port1: input_signal, port2: output_signal};

D. module_name -> (port1=input_signal, port2=output_signal);

Solution

1. Step 1: Recall named port connection syntax

   Named connections use dot notation: .port_name(signal_name).

2. Step 2: Match syntax options

   module_name (.port1(input_signal), .port2(output_signal)); matches the correct syntax: module_name (.port1(input_signal), .port2(output_signal));

3. Final Answer:

   module_name (.port1(input_signal), .port2(output_signal)); -> Option B

4. Quick Check:

   Named ports use dot and parentheses [OK]

Hint: Named ports use dot before port name [OK]

Common Mistakes:

• Using commas without dots for named ports
• Using braces or arrows which are invalid
• Confusing named and positional syntax

3. Given the module declaration:

module my_module(input a, input b, output c);

Which instantiation will correctly connect signals x, y, and z by position?

medium

A. my_module instance1 (.a(x), .b(y), .c(z));

B. my_module instance1 (z, y, x);

C. my_module instance1 (x, y, z);

D. my_module instance1 (.c(z), .b(y), .a(x));

Solution

1. Step 1: Understand port order in module

   The ports are declared in order: a, b, c.

2. Step 2: Match signals by position

   By position, the first signal connects to 'a', second to 'b', third to 'c'. So (x, y, z) matches correctly.

3. Final Answer:

   my_module instance1 (x, y, z); -> Option C

4. Quick Check:

   Position order = a=x, b=y, c=z [OK]

Hint: Position order matches port declaration order [OK]

Common Mistakes:

• Swapping signal order in positional connection
• Using named syntax but calling it positional
• Connecting signals in wrong order

4. Identify the error in this module instantiation:

my_module instance1 (x, .b(y), z);

Assuming my_module ports are a, b, c in order.

medium

A. Mixing positional and named connections is not allowed.

B. The named connection .b(y) is correct here.

C. The order of signals is correct for positional connection.

D. No error; this is valid syntax.

Solution

1. Step 1: Check connection styles used

   The instantiation mixes positional (x, z) and named (.b(y)) connections.

2. Step 2: Recall Verilog rules on mixing connections

   Verilog does not allow mixing positional and named port connections in the same instantiation.

3. Final Answer:

   Mixing positional and named connections is not allowed. -> Option A

4. Quick Check:

   Mixing connection styles = error [OK]

Hint: Do not mix named and positional in one instantiation [OK]

Common Mistakes:

• Thinking mixed connections are allowed
• Ignoring order importance in positional connections
• Assuming named connections can appear anywhere

5. You have a module with ports declared as (input clk, input reset, output reg done). You want to instantiate it with signals clk_sig, rst_sig, and done_sig. Which instantiation style is safer and why?

hard

A. By name, because it explicitly connects signals to ports regardless of order.

B. By position, because it is shorter and easier to write.

C. By position, because it allows skipping some ports.

D. By name, because it automatically matches signals by data type.

Solution

1. Step 1: Consider risks of positional connection

   Positional connection depends on port order; if order changes, connections break.

2. Step 2: Consider benefits of named connection

   Named connection explicitly links signals to port names, so order changes do not cause errors.

3. Final Answer:

   By name, because it explicitly connects signals to ports regardless of order. -> Option A

4. Quick Check:

   Named connection = safer for clarity [OK]

Hint: Use named ports to avoid order mistakes [OK]

Common Mistakes:

• Assuming positional is always simpler and safer
• Thinking named connection matches by data type
• Believing positional allows skipping ports