Port connection by name vs by position in Verilog - Practice Questions

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of module instantiation by position

What is the output of the following Verilog code when the module test_module is instantiated by position?

Verilog

module test_module(input wire a, input wire b, output wire y);
  assign y = a & b;
endmodule

module top;
  reg x1 = 1'b1;
  reg x2 = 1'b0;
  wire out;

  test_module inst(x1, x2, out);

  initial begin
    $display("Output: %b", out);
  end
endmodule

A Output: 1

B Output: 0

C Output: x

D Compilation error

💡 Hint

Remember that port connections by position match ports in the order they are declared in the module.

The module test_module has ports a, b, and y in that order. The instantiation connects x1 to a (1), x2 to b (0), so output y is 1 & 0 = 0.

❓ Predict Output

intermediate

Output of module instantiation by name

What is the output of the following Verilog code when the module test_module is instantiated by name?

Verilog

module test_module(input wire a, input wire b, output wire y);
  assign y = a | b;
endmodule

module top;
  reg x1 = 1'b0;
  reg x2 = 1'b1;
  wire out;

  test_module inst(.b(x2), .a(x1), .y(out));

  initial begin
    $display("Output: %b", out);
  end
endmodule

A Compilation error

B Output: 0

C Output: x

D Output: 1

💡 Hint

Port connections by name allow you to connect ports in any order.

The module test_module has ports a and b. The instantiation connects b to x2 (1) and a to x1 (0). The output y is a | b = 0 | 1 = 1.

❓ Predict Output

advanced

Effect of swapping port order in positional connection

Given the module mod below, what is the output when instantiated with swapped inputs by position?

Verilog

module mod(input wire a, input wire b, output wire y);
  assign y = a ^ b;
endmodule

module top;
  reg p = 1'b1;
  reg q = 1'b0;
  wire result;

  mod instance(q, p, result);

  initial begin
    $display("Result: %b", result);
  end
endmodule

A Result: 1

B Result: 0

C Result: x

D Compilation error

💡 Hint

Positional connections depend on the order of ports in the module declaration.

The module expects a then b. The instantiation passes q=0 as a and p=1 as b. XOR of 0 and 1 is 1.

❓ Predict Output

advanced

Error when mixing positional and named port connections

What error occurs when mixing positional and named port connections in this instantiation?

Verilog

module example(input wire a, input wire b, output wire y);
  assign y = a & b;
endmodule

module top;
  reg x = 1'b1;
  reg z = 1'b0;
  wire out;

  example inst(.b(z), x, .y(out));

  initial begin
    $display("Out: %b", out);
  end
endmodule

A Syntax error: positional arguments must come before named arguments

B Output: 0

C No error, output: 0

D Output: 1

💡 Hint

In Verilog, positional port connections must come before any named connections.

Verilog requires that all positional port connections precede any named port connections in a module instantiation. In this example, the instantiation starts with a named connection `.b(z)`, followed by a positional connection `x`, which violates this rule and results in a syntax error.

🧠 Conceptual

expert

Why prefer named port connections in large modules?

Which reason best explains why named port connections are preferred over positional connections in large Verilog modules?

A Positional connections are deprecated and no longer supported

B Named connections always use less memory in hardware

C Named connections reduce errors by explicitly matching ports regardless of order

D Named connections execute faster during simulation

💡 Hint

Think about how easy it is to make mistakes when connecting many ports.

Named port connections explicitly specify which signal connects to which port, reducing errors from incorrect ordering. Positional connections rely on order, which can cause bugs in large modules.

Practice

1. What is the main difference between port connection by name and port connection by position in Verilog?

easy

A. By position allows skipping ports; by name does not allow skipping ports.

B. By position connects ports explicitly by their names; by name connects ports in the order declared.

C. By name requires fewer ports; by position requires all ports to be connected.

D. By name connects ports explicitly by their names; by position connects ports in the order declared.

Solution

1. Step 1: Understand port connection by position

   Port connection by position links signals to ports based on the order the ports are declared in the module.

2. Step 2: Understand port connection by name

   Port connection by name links signals explicitly by specifying the port names, so order does not matter.

3. Final Answer:

   By name connects ports explicitly by their names; by position connects ports in the order declared. -> Option D

4. Quick Check:

   Port connection by name = explicit naming [OK]

Hint: Remember: name = explicit, position = order [OK]

Common Mistakes:

• Confusing order with explicit naming
• Thinking by position allows skipping ports
• Assuming by name requires fewer ports

2. Which of the following is the correct syntax for connecting ports by name in Verilog?

easy

A. module_name (input_signal, output_signal);

B. module_name (.port1(input_signal), .port2(output_signal));

C. module_name {port1: input_signal, port2: output_signal};

D. module_name -> (port1=input_signal, port2=output_signal);

Solution

1. Step 1: Recall named port connection syntax

   Named connections use dot notation: .port_name(signal_name).

2. Step 2: Match syntax options

   module_name (.port1(input_signal), .port2(output_signal)); matches the correct syntax: module_name (.port1(input_signal), .port2(output_signal));

3. Final Answer:

   module_name (.port1(input_signal), .port2(output_signal)); -> Option B

4. Quick Check:

   Named ports use dot and parentheses [OK]

Hint: Named ports use dot before port name [OK]

Common Mistakes:

• Using commas without dots for named ports
• Using braces or arrows which are invalid
• Confusing named and positional syntax

3. Given the module declaration:

module my_module(input a, input b, output c);

Which instantiation will correctly connect signals x, y, and z by position?

medium

A. my_module instance1 (.a(x), .b(y), .c(z));

B. my_module instance1 (z, y, x);

C. my_module instance1 (x, y, z);

D. my_module instance1 (.c(z), .b(y), .a(x));

Solution

1. Step 1: Understand port order in module

   The ports are declared in order: a, b, c.

2. Step 2: Match signals by position

   By position, the first signal connects to 'a', second to 'b', third to 'c'. So (x, y, z) matches correctly.

3. Final Answer:

   my_module instance1 (x, y, z); -> Option C

4. Quick Check:

   Position order = a=x, b=y, c=z [OK]

Hint: Position order matches port declaration order [OK]

Common Mistakes:

• Swapping signal order in positional connection
• Using named syntax but calling it positional
• Connecting signals in wrong order

4. Identify the error in this module instantiation:

my_module instance1 (x, .b(y), z);

Assuming my_module ports are a, b, c in order.

medium

A. Mixing positional and named connections is not allowed.

B. The named connection .b(y) is correct here.

C. The order of signals is correct for positional connection.

D. No error; this is valid syntax.

Solution

1. Step 1: Check connection styles used

   The instantiation mixes positional (x, z) and named (.b(y)) connections.

2. Step 2: Recall Verilog rules on mixing connections

   Verilog does not allow mixing positional and named port connections in the same instantiation.

3. Final Answer:

   Mixing positional and named connections is not allowed. -> Option A

4. Quick Check:

   Mixing connection styles = error [OK]

Hint: Do not mix named and positional in one instantiation [OK]

Common Mistakes:

• Thinking mixed connections are allowed
• Ignoring order importance in positional connections
• Assuming named connections can appear anywhere

5. You have a module with ports declared as (input clk, input reset, output reg done). You want to instantiate it with signals clk_sig, rst_sig, and done_sig. Which instantiation style is safer and why?

hard

A. By name, because it explicitly connects signals to ports regardless of order.

B. By position, because it is shorter and easier to write.

C. By position, because it allows skipping some ports.

D. By name, because it automatically matches signals by data type.

Solution

1. Step 1: Consider risks of positional connection

   Positional connection depends on port order; if order changes, connections break.

2. Step 2: Consider benefits of named connection

   Named connection explicitly links signals to port names, so order changes do not cause errors.

3. Final Answer:

   By name, because it explicitly connects signals to ports regardless of order. -> Option A

4. Quick Check:

   Named connection = safer for clarity [OK]

Hint: Use named ports to avoid order mistakes [OK]

Common Mistakes:

• Assuming positional is always simpler and safer
• Thinking named connection matches by data type
• Believing positional allows skipping ports