File I/O for test vectors ($readmemh, $writememh) in Verilog - Step-by-Step Execution

Concept Flow - File I/O for test vectors ($readmemh, $writememh)

Start Simulation

↓

$readmemh reads file

↓

Memory array initialized

↓

Simulation runs using memory

↓

$writememh writes memory to file

↓

End Simulation

The simulation starts, reads hex data from a file into memory using $readmemh, runs the test, then writes memory content back to a file with $writememh.

Execution Sample

Verilog

reg [7:0] mem [0:3];
initial begin
  $readmemh("input.hex", mem);
  // simulation code here
  $writememh("output.hex", mem);
end

This code reads hex values from 'input.hex' into a memory array, then writes the memory content to 'output.hex' after simulation.

Execution Table

Step	Action	File Accessed	Memory State	Output
1	Start simulation	N/A	[?, ?, ?, ?]	No output
2	$readmemh loads 'input.hex'	input.hex	[0x1A, 0x2B, 0x3C, 0x4D]	No output
3	Simulation runs using mem	N/A	[0x1A, 0x2B, 0x3C, 0x4D]	No output
4	$writememh writes 'output.hex'	output.hex	[0x1A, 0x2B, 0x3C, 0x4D]	File 'output.hex' created with mem data
5	End simulation	N/A	[0x1A, 0x2B, 0x3C, 0x4D]	No output

💡 Simulation ends after writing memory contents to output file.

Variable Tracker

Variable	Start	After $readmemh	After simulation	Final
mem[0]	?	0x1A	0x1A	0x1A
mem[1]	?	0x2B	0x2B	0x2B
mem[2]	?	0x3C	0x3C	0x3C
mem[3]	?	0x4D	0x4D	0x4D

Key Moments - 3 Insights

Why does mem have '?' before $readmemh runs?

Before $readmemh, memory is uninitialized, so values are unknown (shown as '?'). After $readmemh (see step 2), mem is loaded with file data.

Does $writememh change memory content?

$writememh only writes memory to a file; it does not modify memory values (see step 4).

What happens if 'input.hex' file is missing?

If 'input.hex' is missing, $readmemh will not load data, so mem remains uninitialized or retains previous values, causing simulation errors.

Visual Quiz - 3 Questions

Look at the execution table, what is mem[2] after $readmemh loads 'input.hex'?

A 0x2B

B 0x3C

C ?

D 0x4D

💡 Hint

Check row 2 under 'Memory State' column in execution_table.

At which step does the simulation write memory contents to a file?

A Step 4

B Step 2

C Step 3

D Step 5

💡 Hint

Look for $writememh action in execution_table.

If the input file is missing, what will mem contain after step 2?

A Memory filled with zeros

B Memory filled with ones

C Memory unchanged, possibly '?'

D Memory cleared

💡 Hint

Refer to key_moments about missing input file and step 2 in execution_table.

Concept Snapshot

$readmemh("file", mem) loads hex data from a file into memory array.
$writememh("file", mem) writes memory content to a hex file.
Memory must be declared as an array.
Files must be accessible during simulation.
Useful for test vectors and stimulus data.
Simulation reads input, runs, then writes output data.

Full Transcript

This visual trace shows how Verilog uses $readmemh and $writememh for file input/output of test vectors. The simulation starts with uninitialized memory. Then $readmemh reads hex data from 'input.hex' and loads it into the memory array. The simulation runs using this memory data unchanged. Finally, $writememh writes the memory content to 'output.hex'. The memory values remain stable after loading and writing. If the input file is missing, memory stays uninitialized, which can cause errors. This process helps test hardware designs with real data files.

Practice

1. What is the primary purpose of the Verilog system task $readmemh?

easy

A. To load hexadecimal data from a file into a memory array

B. To write memory contents to a file in binary format

C. To initialize registers with random values

D. To display memory contents on the console

Solution

1. Step 1: Understand $readmemh usage

   $readmemh is used to read hexadecimal data from a file and load it into a memory array in Verilog.

2. Step 2: Compare with other options

   Other options describe writing data, random initialization, or display, which are not the purpose of $readmemh.

3. Final Answer:

   To load hexadecimal data from a file into a memory array -> Option A

4. Quick Check:

   $readmemh loads hex data [OK]

Hint: Remember: $readmemh reads hex data into memory [OK]

Common Mistakes:

• Confusing $readmemh with $writememh
• Thinking it writes data instead of reading
• Assuming it reads binary instead of hex

2. Which of the following is the correct syntax to write memory contents to a hex file in Verilog?

easy

A. $readmemh("data.hex", mem_array);

B. $writememh("output.hex", mem_array);

C. $writehex("output.hex", mem_array);

D. $dumpmemh("output.hex", mem_array);

Solution

1. Step 1: Identify the correct system task for writing

   $writememh is the Verilog system task used to write memory contents to a hex file.

2. Step 2: Check syntax correctness

   The syntax $writememh("output.hex", mem_array); correctly specifies the file name and memory array.

3. Final Answer:

   $writememh("output.hex", mem_array); -> Option B

4. Quick Check:

   Write memory to hex file = $writememh [OK]

Hint: Use $writememh to save memory to hex file [OK]

Common Mistakes:

• Using $readmemh instead of $writememh
• Misspelling the system task name
• Using non-existent tasks like $writehex

3. Given the following Verilog code snippet, what will be the content of mem[0] after $readmemh executes if the file data.hex contains:
0A
1F
2B

reg [7:0] mem [0:2];
initial begin
  $readmemh("data.hex", mem);
end

medium

A. 8'h00

B. 8'h1F

C. 8'h2B

D. 8'h0A

Solution

1. Step 1: Understand $readmemh file loading order

   $readmemh loads the first line of the file into mem[0], second line into mem[1], and so on.

2. Step 2: Match file content to memory

   The first line is 0A, so mem[0] will be 8'h0A.

3. Final Answer:

   8'h0A -> Option D

4. Quick Check:

   First file line -> mem[0] = 0A [OK]

Hint: First file line loads into mem[0] with $readmemh [OK]

Common Mistakes:

• Assuming mem[0] gets last file line
• Confusing hex values with decimal
• Forgetting zero-based indexing

4. Identify the error in the following Verilog code snippet that attempts to write memory contents to a hex file:

reg [7:0] mem [0:3];
initial begin
  $writememh(mem, "output.hex");
end

medium

A. Missing file extension in filename

B. Memory array size is invalid

C. Arguments to $writememh are in wrong order

D. Cannot use $writememh inside initial block

Solution

1. Step 1: Check $writememh argument order

   The correct syntax is $writememh("filename", memory_array);. The code reverses these arguments.

2. Step 2: Verify other aspects

   Memory size and file extension are valid, and $writememh can be used inside initial blocks.

3. Final Answer:

   Arguments to $writememh are in wrong order -> Option C

4. Quick Check:

   Filename first, memory second in $writememh [OK]

Hint: Filename is first argument in $writememh [OK]

Common Mistakes:

• Swapping filename and memory array arguments
• Thinking file extension is mandatory
• Believing $writememh can't be in initial block

5. You want to test a memory module by loading test vectors from a hex file and then save the modified memory contents back to another hex file. Which sequence of Verilog system tasks correctly achieves this?

hard

A. $readmemh("input.hex", mem); // test$writememh("output.hex", mem); // save

B. $writememh("input.hex", mem); // test$readmemh("output.hex", mem); // save

C. $readmemh(mem, "input.hex"); // test$writememh(mem, "output.hex"); // save

D. $readmemh("output.hex", mem); // test$writememh("input.hex", mem); // save

Solution

1. Step 1: Load test vectors correctly

   Use $readmemh("input.hex", mem); to load test vectors from the input file into memory.

2. Step 2: Save modified memory correctly

   Use $writememh("output.hex", mem); to write the memory contents to the output file.

3. Final Answer:

   $readmemh("input.hex", mem); // test
   $writememh("output.hex", mem); // save -> Option A

4. Quick Check:

   Read first, then write with correct syntax [OK]

Hint: Read test vectors first, write results second [OK]

Common Mistakes:

• Reversing read and write order
• Swapping filename and memory arguments
• Using wrong filenames for read/write